Ij

PIC16F684
Data Sheet
14-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
nanoWatt Technology
Preliminary
2004 Microchip Technology Inc.
DS41202C
Note the following details of the code protection feature on Microchip devices:
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Microchip products meet the specification contained in their particular Microchip Data Sheet.
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Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
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There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
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Microchip is willing to work with the customer who is concerned about the integrity of their code.
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Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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Information contained in this publication regarding device
Trademarks
applications and the like is intended through suggestion only
The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
No representation or warranty is given and no liability is
registered trademarks of Microchip Technology Incorporated
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to the accuracy or use of such information, or infringement of
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with express written approval by Microchip. No licenses are
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Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
property rights.
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
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All other trademarks mentioned herein are property of their
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? 2004, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company's quality system processes and
procedures are for its PICmicro? 8-bit MCUs, KEELOQ? code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip's quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Preliminary
2004 Microchip Technology Inc.
DS41202C-page ii
PIC16F684
14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
High-Performance RISC CPU:
Low-Power Features:
? Only 35 instructions to learn:
? Standby Current:
- All single-cycle instructions except branches
- 1 nA @ 2.0V, typical
? Operating speed:
? Operating Current:
- 8.5 ?A @ 32 kHz, 2.0V, typical
- DC ? 20 MHz oscillator/clock input
- 100 ?A @ 1 MHz, 2.0V, typical
- DC ? 200 ns instruction cycle
? Interrupt capability
? Watchdog Timer Current:
- 1 ?A @ 2.0V, typical
? 8-level deep hardware stack
? Direct, Indirect and Relative Addressing modes
Peripheral Features:
Special Microcontroller Features:
? 12 I/O pins with individual direction control:
? Precision Internal Oscillator:
- High current source/sink for direct LED drive
- Interrupt-on-pin change
- Factory calibrated to ?1%
- Individually programmable weak pull-ups
- Software selectable frequency range of
- Ultra Low-power Wake-up (ULPWU)
8 MHz to 31 kHz
- Software tunable
? Analog comparator module with:
- Two-speed Start-up mode
- Two analog comparators
- Crystal fail detect for critical applications
- Programmable on-chip voltage reference
- Clock mode switching during operation for
(CVREF) module (% of VDD)
power savings
- Comparator inputs and outputs externally
accessible
? Power-saving Sleep mode
? A/D Converter:
? Wide operating voltage range (2.0V-5.5V)
- 10-bit resolution and 8 channels
? Industrial and Extended Temperature range
? Timer0: 8-bit timer/counter with 8-bit
? Power-on Reset (POR)
programmable prescaler
? Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
? Enhanced Timer1:
? Brown-out Detect (BOD) with software control
- 16-bit timer/counter with prescaler
option
- External Gate Input mode
- Option to use OSC1 and OSC2 in LP mode
? Enhanced low-current Watchdog Timer (WDT)
as Timer1 oscillator if INTOSC mode
with on-chip oscillator (software selectable
selected
nominal 268 seconds with full prescaler) with
software enable
? Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
? Multiplexed Master Clear with pull-up/input pin
? Enhanced Capture, Compare, PWM module:
? Programmable code protection
- 16-bit Capture, max resolution 12.5 ns
? High Endurance Flash/EEPROM cell:
- Compare, max resolution 200 ns
- 100,000 write Flash endurance
- 10-bit PWM with 1, 2 or 4 output channels,
- 1,000,000 write EEPROM endurance
programmable "dead time", max frequency
- Flash/Data EEPROM retention: > 40 years
20 kHz
? In-Circuit Serial ProgrammingTM (ICSPTM) via two
pins
Program
Data Memory
Memory
10-bit A/D
Timers
Device
I/O
Comparators
(ch)
8/16-bit
Flash
SRAM
EEPROM
(words)
(bytes)
(bytes)
PIC16F684
2048
128
256
12
8
2
2/1
Preliminary
2004 Microchip Technology Inc.
DS41202C-page 1
PIC16F684
Pin Diagram
14-pin PDIP, SOIC, TSSOP
1
VDD
14
VSS
RA5/T1CKI/OSC1/CLKIN
2
RA0/AN0/C1IN+/ICSPDAT/ULPWU
13
RA4/AN3/T1G/OSC2/CLKOUT
RA1/AN1/C1IN-/VREF/ICSPCLK
3
12
RA3/MCLR/VPP
RA2/AN2/T0CKI/INT/C1OUT
4
11
RC5/CCP1/P1A
RC0/AN4/C2IN+
5
10
RC4/C2OUT/P1B
RC1/AN5/C2IN-
6
9
RC3/AN7/P1C
RC2/AN6/P1D
7
8
Preliminary
2004 Microchip Technology Inc.
DS41202C-page 2
PIC16F684
Table of Contents
1.0  Device Overview ......................................................................................................................................................................... 5
2.0  Memory Organization .................................................................................................................................................................. 7
3.0  Clock Sources ........................................................................................................................................................................... 19
4.0  I/O Ports .................................................................................................................................................................................... 31
5.0  Timer0 Module .......................................................................................................................................................................... 45
6.0  Timer1 Module with Gate Control.............................................................................................................................................. 49
7.0  Timer2 Module .......................................................................................................................................................................... 53
8.0  Comparator Module................................................................................................................................................................... 55
9.0  Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 63
10.0 Data EEPROM Memory ............................................................................................................................................................ 71
11.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................. 75
12.0 Special Features of the CPU..................................................................................................................................................... 91
13.0 Instruction Set Summary ......................................................................................................................................................... 111
14.0 Development Support.............................................................................................................................................................. 121
15.0 Electrical Specifications........................................................................................................................................................... 127
16.0 DC and AC Characteristics Graphs and Tables...................................................................................................................... 147
17.0 Packaging Information............................................................................................................................................................. 149
Appendix A: Data Sheet Revision History......................................................................................................................................... 153
Appendix B: Migrating from other PICmicro? Devices ..................................................................................................................... 153
Index ................................................................................................................................................................................................. 155
On-Line Support................................................................................................................................................................................ 159
Systems Information and Upgrade Hot Line ..................................................................................................................................... 159
Reader Response ............................................................................................................................................................................. 160
Product Identification System ........................................................................................................................................................... 161
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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Preliminary
2004 Microchip Technology Inc.
DS41202C-page 3
PIC16F684
NOTES:
Preliminary
2004 Microchip Technology Inc.
DS41202C-page 4
PIC16F684
1.0
DEVICE OVERVIEW
The reference manual should be considered a comple-
mentary document to this data sheet and is highly
This document contains device specific information for
recommended reading for a better understanding of the
the PIC16F684. Additional information may be found in
device architecture and operation of the peripheral
the "PICmicro? Mid-Range MCU Family Reference
modules.
Manual" (DS33023), which may be obtained from your
The PIC16F684 is covered by this data sheet. It is
local Microchip Sales Representative or downloaded
available in 14-pin PDIP, SOIC and TSSOP packages.
from the Microchip web site.
Figure 1-1 shows a block diagram of the PIC16F684
device. Table 1-1 shows the pinout description.
FIGURE 1-1:
PIC16F684 BLOCK DIAGRAM
INT
Configuration
13
8
PORTA
Data Bus
Program Counter
RA0
Flash
RA1
2k X 14
RA2
Program
RAM
Memory
RA3
8-Level Stack
128 Bytes
File
(13-Bit)
RA4
Registers
RA5
Program
14
RAM Addr
9
Bus
Addr MUX
Instruction Reg
PORTC
Indirect
7
Direct Addr
8
Addr
RC0
RC1
FSR Reg
RC2
RC3
Status Reg
8
RC4
RC5
3
MUX
Power-up
Timer
Instruction
Oscillator
Decode &
Start-up Timer
ALU
Control
Power-on
8
Reset
Timing
Watchdog
OSC1/CLKIN
W Reg
Generation
Timer
Brown-out
OSC2/CLKOUT
Detect
Internal
Oscillator
Block
CCP1/P1A P1B P1C P1D
T1G
MCLR VDD
VSS
T1CKI
Timer0
Timer1
Timer2
ECCP
T0CKI
2 Analog Comparators
EEDATA
Analog-To-Digital Converter
and Reference
8 256 Bytes
Data
EEPROM
EEADDR
VREF
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
Preliminary
2004 Microchip Technology Inc.
DS41202C-page 5
PIC16F684
TABLE 1-1:
PIC16F684 PINOUT DESCRIPTION
Input
Output
Name
Function
Description
Type
Type
RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA0
TTL
CMOS
PORTA I/O w/programmable pull-up and interrupt-on-change
AN0
AN
--
A/D Channel 0 input
C1IN+
AN
--
Comparator 1 input
ICSPDAT
TTL
CMOS
Serial Programming Data I/O
ULPWU
AN
--
Ultra Low-power Wake-up input
RA1/AN1/C1IN-/VREF/ICSPCLK
RA1
TTL
CMOS
PORTA I/O w/programmable pull-up and interrupt-on-change
AN1
AN
--
A/D Channel 1 input
C1IN-
AN
--
Comparator 1 input
AN
--
External Voltage Reference for A/D
VREF
ICSPCLK
ST
--
Serial Programming Clock
RA2/AN2/T0CKI/INT/C1OUT
RA2
ST
CMOS
PORTA I/O w/programmable pull-up and interrupt-on-change
AN2
AN
--
A/D Channel 2 input
T0CKI
ST
--
Timer0 clock input
INT
ST
--
External Interrupt
C1OUT
--
CMOS
Comparator 1 output
RA3/MCLR/VPP
RA3
TTL
--
PORTA input with interrupt-on-change
MCLR
ST
--
Master Clear w/internal pull-up
HV
--
Programming voltage
VPP
RA4/AN3/T1G/OSC2/CLKOUT
RA4
TTL
CMOS
PORTA I/O w/programmable pull-up and interrupt-on-change
AN3
AN
--
A/D Channel 3 input
ST
--
Timer1 gate
T1G
OSC2
--
XTAL
Crystal/Resonator
FOSC/4 output
CLKOUT
--
CMOS
RA5/T1CKI/OSC1/CLKIN
RA5
TTL
CMOS
PORTA I/O w/programmable pull-up and interrupt-on-change
T1CKI
ST
--
Timer1 clock
OSC1
XTAL
--
Crystal/Resonator
CLKIN
ST
--
External clock input/RC oscillator connection
RC0/AN4/C2IN+
RC0
TTL
CMOS
PORTC I/O
AN4
AN
--
A/D Channel 4 input
C2IN+
AN
--
Comparator 2 input
RC1/AN5/C2IN-
RC1
TTL
CMOS
PORTC I/O
AN5
AN
--
A/D Channel 5 input
C2IN-
AN
--
Comparator 2 input
RC2/AN6/P1D
RC2
TTL
CMOS
PORTC I/O
AN6
AN
--
A/D Channel 6 input
P1D
--
CMOS
PWM output
RC3/AN7/P1C
RC3
TTL
CMOS
PORTC I/O
AN7
AN
--
A/D Channel 7 input
P1C
--
CMOS
PWM output
RC4/C2OUT/P1B
RC4
TTL
CMOS
PORTC I/O
C2OUT
--
CMOS
Comparator 2 output
P1B
--
CMOS
PWM output
RC5/CCP1/P1A
RC5
TTL
CMOS
PORTC I/O
CCP1
ST
CMOS
Capture input/Compare output
P1A
--
CMOS
PWM output
VSS
Power
--
Ground reference
VSS
VDD
Power
--
Positive supply
VDD
Legend:
TTL = TTL input buffer, ST = Schmitt Trigger input buffer, AN = Analog input
Preliminary
2004 Microchip Technology Inc.
DS41202C-page 6
PIC16F684
2.0
MEMORY ORGANIZATION
2.2
Data Memory Organization
The data memory (see Figure 2-2) is partitioned into
2.1
Program Memory Organization
two banks, which contain the General Purpose Regis-
ters (GPR) and the Special Function Registers (SFR).
The PIC16F684 has a 13-bit program counter capable
The Special Function Registers are located in the first
of addressing an 8k x 14 program memory space. Only
32 locations of each bank. Register locations 20h-7Fh
the first 2k x 14 (0000h-07FFh) for the PIC16F684 is
in Bank 0 and A0h-BFh in Bank 1 are General Purpose
physically implemented. Accessing a location above
Registers, implemented as static RAM. Register
these boundaries will cause a wrap around within the
locations F0h-FFh in Bank 1 point to addresses
first 2k x 14 space. The Reset vector is at 0000h and
70h-7Fh in Bank 0. All other RAM is unimplemented
the interrupt vector is at 0004h (see Figure 2-1).
and returns `0' when read. RP0 (Status<5>) is the bank
select bit.
FIGURE 2-1:
PROGRAM MEMORY MAP
RP0 = 0: Bank 0 is selected
AND STACK FOR THE
RP0 = 1: Bank 1 is selected
PIC16F684
Note:
The IRP and RP1 bits Status<7:6> are
PC<12:0>
reserved  and  should  always  be
CALL, RETURN
13
maintained as `0's.
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
000h
Interrupt Vector
0004
0005
On-chip Program
Memory
07FFh
0800h
1FFFh
Preliminary
2004 Microchip Technology Inc.
DS41202C-page 7
PIC16F684
2.2.1
GENERAL PURPOSE REGISTER
FIGURE 2-2:
DATA MEMORY MAP OF
FILE
THE PIC16F684
The register file is organized as 128 x 8 in the
File
File
PIC16F684. Each register is accessed, either directly
Address
Address
or indirectly, through the File Select Register (FSR)
Indirect Addr.(1)
Indirect Addr.(1)
00h
80h
(see Section 2.4 "Indirect Addressing, INDF and
TMR0
01h
OPTION_REG
81h
FSR Registers").
02h
82h
PCL
PCL
STATUS
03h
STATUS
83h
2.2.2
SPECIAL FUNCTION REGISTERS
FSR
04h
FSR
84h
The Special Function Registers are registers used by
05h
PORTA
TRISA
85h
the CPU and peripheral functions for controlling the
06h
86h
desired operation of the device (see Table 2-1). These
PORTC
TRISC
07h
87h
registers are static RAM.
08h
88h
The special registers can be classified into two sets:
09h
89h
core and peripheral. The Special Function Registers
PCLATH
PCLATH
0Ah
8Ah
associated with the "core" are described in this section.
INTCON
INTCON
0Bh
8Bh
Those related to the operation of the peripheral
PIR1
PIE1
0Ch
8Ch
features are described in the section of that peripheral
0Dh
8Dh
feature.
TMR1L
PCON
0Eh
8Eh
OSCCON
TMR1H
0Fh
8Fh
OSCTUNE
T1CON
10h
90h
TMR2
ANSEL
11h
91h
PR2
T2CON
12h
92h
CCPR1L
13h
93h
CCPR1H
14h
94h
CCP1CON
WPUA
15h
95h
PWM1CON
IOCA
16h
96h
ECCPAS
17h
97h
WDTCON
18h
98h
CMCON0
VRCON
19h
99h
CMCON1
EEDAT
1Ah
9Ah
EEADR
1Bh
9Bh
EECON1
1Ch
9Ch
(1)
EECON2
1Dh
9Dh
ADRESH
ADRESL
1Eh
9Eh
ADCON0
ADCON1
1Fh
9Fh
General
A0h
20h
Purpose
Registers
32 Bytes
BFh
General
Purpose
Registers
96 Bytes
F0h
ACCESSES 70h-7Fh
7Fh
FFh
BANK 0
BANK 1
Unimplemented data memory locations, read as `0'.
Note 1:
Not a physical register.
Preliminary
2004 Microchip Technology Inc.
DS41202C-page 8
PIC16F684
TABLE 2-1:
PIC16F684 SPECIAL REGISTERS SUMMARY BANK 0
Value on
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
POR, BOD
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
17, 99
xxxx xxxx
01h
TMR0
Timer0 Module's register
45, 99
xxxx xxxx
02h
PCL
Program Counter's (PC) Least Significant Byte
17, 99
0000 0000
IRP(1)
RP1(1)
03h
STATUS
RP0
TO
PD
Z
DC
C
11, 99
0001 1xxx
04h
FSR
Indirect Data Memory Address Pointer
17, 99
xxxx xxxx
--
--
RA5
RA4
RA3
RA2
RA1
RA0
31, 99
05h
PORTA
--xx xxxx
06h
--
Unimplemented
--
--
07h
PORTC
--
--
RC5
RC4
RC3
RC2
RC1
RC0
40, 99
--xx xxxx
08h
--
Unimplemented
--
--
09h
--
Unimplemented
--
--
0Ah
PCLATH
--
--
--
Write Buffer for upper 5 bits of Program Counter
17, 99
---0 0000
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
13, 99
0000 0000
0Ch
PIR1
EEIF
ADIF
CCP1IF
C2IF
C1IF
OSFIF
TMR2IF
TMR1IF
15, 99
0000 0000
0Dh
--
Unimplemented
--
--
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1
49, 99
xxxx xxxx
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1
49, 99
xxxx xxxx
51, 99
0000 0000
10h
T1CON
T1GINV
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
11h
TMR2
Timer2 Module register
53, 99
0000 0000
12h
T2CON
--
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
53, 99
-000 0000
13h
75, 99
XXXX XXXX
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
14h
75, 99
XXXX XXXX
CCPR1H
Capture/Compare/PWM Register 1 High Byte
15h
75, 99
0000 0000
CCP1CON
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
16h
85, 99
0000 0000
PWM1CON
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
17h
86, 99
0000 0000
ECCPAS
ECCPASE
ECCPAS2
ECCPAS1
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0
18h
WDTCON
WDTPS3
WDTPS2
WDTPS1
WDTPS0
SWDTEN
106, 99
---0 1000
--
--
--
C2INV
C1INV
CIS
CM2
CM1
CM0
55, 99
19h
CMCON0
C2OUT
C1OUT
0000 0000
1Ah
CMCON1
--
--
--
--
--
--
T1GSS
C2SYNC
59, 99
---- --10
1Bh
--
Unimplemented
--
--
1Ch
--
Unimplemented
--
--
1Dh
--
Unimplemented
--
--
1Eh
ADRESH
Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
65, 99
xxxx xxxx
66, 99
00-0 0000
1Fh
ADCON0
ADFM
VCFG
--
CHS2
CHS1
CHS0
GO/DONE
ADON
Legend:
-- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded =
unimplemented
Note 1:
IRP and RP1 bits are reserved, always maintain these bits clear.
Preliminary
2004 Microchip Technology Inc.
DS41202C-page 9
PIC16F684
TABLE 2-2:
PIC16F684 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
POR, BOD
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
17, 99
xxxx xxxx
81h
OPTION_REG
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
12, 99
1111 1111
82h
PCL
Program Counter's (PC) Least Significant Byte
17, 99
0000 0000
IRP(1)
RP1(1)
83h
STATUS
RP0
TO
PD
Z
DC
C
11, 99
0001 1xxx
84h
FSR
Indirect Data Memory Address Pointer
17, 99
xxxx xxxx
--
--
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
32, 99
85h
TRISA
--11 1111
86h
--
Unimplemented
--
--
87h
TRISC
--
--
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
43, 99
--11 1111
88h
--
Unimplemented
--
--
89h
--
Unimplemented
--
--
8Ah
PCLATH
--
--
--
Write Buffer for upper 5 bits of Program Counter
17, 99
---0 0000
8Bh
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
13, 99
0000 0000
8Ch
PIE1
EEIE
ADIE
CCP1IE
C2IE
C1IE
OSFIE
TMR2IE
TMR1IE
14, 99
0000 0000
8Dh
--
Unimplemented
--
--
8Eh
PCON
--
--
ULPWUE
SBODEN
--
--
POR
BOD
16, 99
--01 --qq
OSTS(2)
8Fh
OSCCON
--
IRCF2
IRCF1
IRCF0
HTS
LTS
SCS
29, 99
-110 x000
90h
OSCTUNE
--
--
--
TUN4
TUN3
TUN2
TUN1
TUN0
23, 99
---0 0000
91h
ANSEL
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
65, 99
1111 1111
92h
PR2
Timer2 Module Period Register
53, 99
1111 1111
93h
--
Unimplemented
--
--
94h
--
Unimplemented
--
--
WPUA(3)
95h
--
--
WPUA5
WPUA4
--
WPUA2
WPUA1
WPUA0
32, 100
--11 -111
96h
IOCA
--
--
IOCA5
IOCA4
IOCA3
IOCA2
IOCA1
IOCA0
33, 100
--00 0000
97h
--
Unimplemented
--
--
98h
--
Unimplemented
--
--
99h
VRCON
VREN
--
VRR
--
VR3
VR2
VR1
VR0
62, 100
0-0- 0000
9Ah
EEDAT
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
EEDAT2
EEDAT1
EEDAT0
71, 100
0000 0000
9Bh
EEADR
EEADR7
EEADR6
EEADR5
EEADR4
EEADR3
EEADR2
EEADR1
EEADR0
71, 100
0000 0000
9Ch
EECON1
--
--
--
--
WRERR
WREN
WR
RD
72, 100
---- x000
9Dh
EECON2
EEPROM Control Register 2 (not a physical register)
72, 100
---- ----
9Eh
ADRESL
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
65, 100
xxxx xxxx
9Fh
ADCON1
--
ADCS2
ADCS1
ADCS0
--
--
--
--
66, 100
-000 ----
Legend:
-- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note  1:
IRP and RP1 bits are reserved, always maintain these bits clear.
2:
OSTS bit OSCCON <3> reset to `0' with Dual Speed Start-up and LP, HS or XT selected as the oscillator.
3:
RA3 pull-up is enabled when MCLRE is `1' in the Configuration Word register.
Preliminary
2004 Microchip Technology Inc.
DS41202C-page 10
PIC16F684
2.2.2.1
Status Register
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the Status register as
The Status register, shown in Register 2-1, contains:
`000u u1uu' (where u = unchanged).
? the arithmetic status of the ALU
It is recommended, therefore, that only BCF, BSF,
? the Reset status
SWAPF and MOVWF instructions are used to alter the
? the bank select bits for data memory (SRAM)
Status register, because these instructions do not affect
any Status bits. For other instructions not affecting any
The Status register can be the destination for any
Status bits, see the "Instruction Set Summary".
instruction, like any other register. If the Status register
is the destination for an instruction that affects the Z,
Note 1: Bits IRP and RP1 (Status<7:6>) are not
DC or C bits, then the write to these three bits is dis-
used by the PIC16F684 and should be
abled. These bits are set or cleared according to the
maintained as clear. Use of these bits is
device logic. Furthermore, the TO and PD bits are not
not recommended, since this may affect
writable. Therefore, the result of an instruction with the
upward compatibility with future products.
Status register as destination may be different than
2: The C and DC bits operate as a Borrow
intended.
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1:
STATUS ? STATUS REGISTER (ADDRESS: 03h OR 83h)
Reserved Reserved
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
bit 7
bit 0
bit 7
IRP: This bit is reserved and should be maintained as `0'
bit 6
RP1: This bit is reserved and should be maintained as `0'
bit 5
RP0: Register Bank Select bit (used for direct addressing)
1 = Bank 1 (80h ? FFh)
0 = Bank 0 (00h ? 7Fh)
TO: Time-out bit
bit 4
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
For borrow, the polarity is reversed.
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the two's
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high-order or low-order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as `0'
-n = Value at POR
`1' = Bit is set
`0' = Bit is cleared
x = Bit is unknown
Preliminary
2004 Microchip Technology Inc.
DS41202C-page 11
PIC16F684
2.2.2.2
Option Register
Note:
To achieve a 1:1 prescaler assignment for
The Option register is a readable and writable register,
TMR0, assign the prescaler to the WDT by
which contains various control bits to configure:
setting PSA bit to `1' (OPTION_REG<3>).
?
TMR0/WDT prescaler
See Section 5.4 "Prescaler".
?
External RA2/INT interrupt
?
TMR0
?
Weak pull-ups on PORTA
REGISTER 2-2:
OPTION_REG ? OPTION REGISTER (ADDRESS: 81h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
RAPU: PORTA Pull-up Enable bit
bit 7
1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RA2/INT pin
0 = Interrupt on falling edge of RA2/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA2/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA2/T0CKI pin
0 = Increment on low-to-high transition on RA2/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS<2:0>: Prescaler Rate Select bits
BIT VALUE
TMR0 RATE
WDT RATE
000
1:2
1:1
1:4
001
1:2
1:8
010
1:4
1 : 16
011
1:8
1 : 32
100
1 : 16
1 : 64
101
1 : 32
1 : 128
110
1 : 64
111
1 : 256
1 : 128
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as `0'
-n = Value at POR
`1' = Bit is set
`0' = Bit is cleared
x = Bit is unknown
Preliminary
2004 Microchip Technology Inc.
DS41202C-page 12
PIC16F684
2.2.2.3
INTCON Register
Note:
Interrupt flag bits are set when an interrupt
The INTCON register is a readable and writable
condition occurs, regardless of the state of
register, which contains the various enable and flag bits
its corresponding enable bit or the global
for TMR0 register overflow, PORTA change and
enable bit, GIE (INTCON<7>). User
external RA2/INT pin interrupts.
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-3:
INTCON ? INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
bit 7
bit 0
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: RA2/INT External Interrupt Enable bit
1 = Enables the RA2/INT external interrupt
0 = Disables the RA2/INT external interrupt
RAIE: PORTA Change Interrupt Enable bit(1)
bit 3
1 = Enables the PORTA change interrupt
0 = Disables the PORTA change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit(2)
bit 2
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RA2/INT External Interrupt Flag bit
1 = The RA2/INT external interrupt occurred (must be cleared in software)