Ij

February 2002
DS0026
Dual High-Speed MOS Driver
General Description
Features
Fast rise and fall times -- 20 ns 1000 pF load
DS0026 is a low cost monolithic high speed two phase MOS
n
clock driver and interface circuit. Unique circuit design pro-
High output swing -- 20V
n
vides both very high speed operation and the ability to drive
High output current drive -- ?1.5 amps
n
large capacitive loads. The device accepts standard TTL
TTL compatible inputs
n
outputs and converts them to MOS logic levels. The device
High rep rate -- 5 to 10 MHz depending on power
n
may be driven from standard 54/74 series and 54S/74S
dissipation
series gates and flip-flops or from drivers such as the
n Low power consumption in MOS "0" state -- 2 mW
DS8830 or DM7440. The DS0026 is intended for applica-
n Drives to 0.4V of GND for RAM address drive
tions in which the output pulse width is logically controlled;
i.e., the output pulse width is equal to the input pulse width.
The DS0026 is designed to fulfill a wide variety of MOS
interface requirements. Information on the correct usage of
the DS0026 in these as well as other systems is included in
the application note AN-76.
Connection Diagram (Top View)
Dual-In-Line Package
00585302
? 2002 National Semiconductor Corporation
DS005853
www.national.com
Absolute Maximum Ratings
Operating Ratings
(Note 1)
If Military/Aerospace specified devices are required,
(V+) - (V-) Differential Voltage
10V to 20V
please contact the National Semiconductor Sales Office/
Maximum Power Dissipation at TA
Distributors for availability and specifications.
= 25?C (Note 7)
1168mW
(V+) - (V-) Differential Voltage
22V
N08E θJA
107?C/W
Input Current
100 mA
N08E θJC
37?C/W
Input Voltage (VIN) - (V-)
5.5V
M08A θJA
180?C/W
Peak Output Current
1.5A
MUA08A θJA
220?C/W
Storage Temperature Range
-65?C to +150?C
Operating Temperature Range, TA
0?C to +70?C
Lead Temperature
(Soldering, 10 sec.)
300?C
Ordering Information
Order Number
Package Type
NS Package Number
DS0026CN
M-DIP
N08E
DS0026CMA
SOIC
M08A
DS0026CMM
MSOP
MUA08A
Electrical Characteristics (Notes 2, 3, 4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
-
VIH
Logic "1" Input Voltage
V = 0V
2
1.5
V
-
IIH
Logic "1" Input Current
VIN - V = 2.4V
10
15
mA
-
VIL
Logic "0" Input Voltage
V = 0V
0.6
0.4
V
-
IIL
Logic "0" Input Current
VIN - V = 0V
-3
-10
?A
-
-
-
VOL
Logic "1" Output Voltage
VIN - V = 2.4V, IOL = 1 mA
V +0.7
V +1.0
V
VIN - V- = 0.4V, VSS V+ + 1.0V
VOH
Logic "0" Output Voltage
V+ - 1.0
V+-0.8
V
IOH = - 1 mA
V+ - V- = 20V, VIN - V- = 2.4V
"ON" Supply Current
ICC(ON)
30
40
mA
(one side on)
V+ - V- = 20V,
ICC(OFF)
"OFF" Supply Current
10
100
?A
VIN - V- = 0V
Switching Characteristics
(TA = 25?C) (Notes 5, 6)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Figure 1)
tON
Turn-On Delay
5
7.5
12
ns
(Figure 2)
11
ns
(Figure 1)
tOFF
Turn-Off Delay
12
15
ns
(Figure 2)
13
ns
tr
Rise Time
CL = 500 pF
15
18
ns
(Figure 1),
(Note 5)
CL = 1000 pF
20
35
ns
CL = 500 pF
30
40
ns
(Figure 2),
(Note 5)
CL = 1000 pF
36
50
ns
tf
Fall Time
CL = 500 pF
12
16
ns
(Figure 1),
(Note 5)
CL = 1000 pF
17
25
ns
CL = 500 pF
28
35
ns
(Figure 2),
(Note 5)
CL = 1000 pF
31
40
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics provides conditions for actual device operation.
Note 2: These specifications apply for V+ - V- = 10V to 20V, CL = 1000 pF, over the temperature range of 0?C to +70?C for the DS0026CN.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
www.national.com
2
Switching Characteristics
(Continued)
Note 4: All typical values for TA = 25?C.
Note 5: Rise and fall time are given for MOS logic levels; i.e., rise time is transition from logic "0" to logic "1" which is voltage fall.
Note 6: The high current transient (as high as 1.5A) through the resistance of the internal interconnecting V- lead during the output transition from the high state
to the low state can appear as negative feedback to the input. If the external interconnecting lead from the driving circuit to V- is electrically long, or has significant
dc resistance, it can subtract from the switching response.
Note 7: Derate N08E package 9.3 mW/?C for TA above 25?C.
Typical VBB Connection
00585308
Typical Performance Characteristics
Turn-On and Turn-Off Delay
Input Current vs Input Voltage
Supply Current vs Temperature
vs Temperature
00585323
00585322
00585324
Rise Time vs Load
Fall Time vs Load
Capacitance
Capacitance
00585326
00585325
3
www.national.com
Typical Performance Characteristics
(Continued)
Recommended Input Coding
DC Power (PDC) vs
Capacitance
Duty Cycle
00585328
00585327
Schematic Diagram
1/2 DS0026
00585310
www.national.com
4
AC Test Circuits and Switching Time Waveforms
00585313
00585312
FIGURE 1.
00585315
00585314
FIGURE 2.
Typical Applications
AC Coupled MOS Clock Driver
00585317
Application Hints
00585316
DC Coupled RAM Memory Address or Precharge
Driver (Positive Supply Only)
DRIVING THE MM5262 WITH THE
DS0026 CLOCK DRIVER
The clock signals for the MM5262 have three requirements
which have the potential of generating problems for the user.
These requirements, high speed, large voltage swing and
large capacitive loads, combine to provide ample opportunity
for inductive ringing on clock lines, coupling clock signals to
other clocks and/or inputs and outputs and generating noise
on the power supplies. All of these problems have the po-
tential of causing the memory system to malfunction. Rec-
ognizing the source and potential of these problems early in
the design of a memory system is the most critical step. The
object here is to point out the source of these problems and
give a quantitative feel for their magnitude.
5
www.national.com
Application Hints
are more expensive than two sided boards. The user must
(Continued)
make the decision as to the necessity of multilayer boards.
Line ringing comes from the fact that at a high enough
Suffice it to say here, that reliable memory boards can be
frequency any line must be considered as a transmission
designed using two sided printed circuit boards.
line with distributed inductance and capacitance. To see how
much ringing can be tolerated we must examine the clock
voltage specification. Figure 3 shows the clock specification,
in diagram form, with idealized ringing sketched in. The
ringing of the clock about the VSS level is particularly critical.
If the VSS - 1 VOH is not maintained, at all times, the
information stored in the memory could be altered. Referring
to Figure 1, if the threshold voltage of a transistor were
-1.3V, the clock going to VSS - 1 would mean that all the
devices, whose gates are tied to that clock, would be only
300 mV from turning on. The internal circuitry needs this
noise margin and from the functional description of the RAM
it is easy to see that turning a clock on at the wrong time can
have disastrous results.
00585318
FIGURE 3. Clock Waveform
Controlling the clock ringing is particularly difficult because of
the relative magnitude of the allowable ringing, compared to
magnitude of the transition. In this case it is 1V out of 20V or
only 5%. Ringing can be controlled by damping the clock
driver and minimizing the line inductance.
00585319
Damping the clock driver by placing a resistance in series
with its output is effective, but there is a limit since it also
FIGURE 4. Clock Waveforms (Voltage and Current)
slows down the rise and fall time of the clock signal. Because
the typical clock driver can be much faster than the worst
Because of the amount of current that the clock driver must
case driver, the damping resistor serves the useful function
supply to its capacitive load, the distribution of power to the
of limiting the minimum rise and fall time. This is very impor-
clock driver must be considered. Figure 4 gives the idealized
tant because the faster the rise and fall times, the worse the
voltage and current waveforms for a clock driver driving a
ringing problem becomes. The size of the damping resistor
1000 pF capacitor with 20 ns rise and fall time.
varies because it is dependent on the details of the actual
As can be seen the current is significant. This current flows
application. It must be determined empirically. In practice a
resistance of 10to 20is usually optimum.
in the VDD and VSS power lines. Any significant inductance in
the lines will produce large voltage transients on the power
Limiting the inductance of the clock lines can be accom-
supplies. A bypass capacitor, as close as possible to the
plished by minimizing their length and by laying out the lines
clock driver, is helpful in minimizing this problem. This by-
such that the return current is closely coupled to the clock
pass is most effective when connected between the VSS and
lines. When minimizing the length of clock lines it is impor-
VDD supplies. The size of the bypass capacitor depends on
tant to minimize the distance from the clock driver output to
the amount of capacitance being driven. Using a low induc-
the furthest point being driven. Because of this, memory
tance capacitor, such as a ceramic or silver mica, is most
boards are usually designed with clock drivers in the center
effective. Another helpful technique is to run the VDD and
of the memory array, rather than on one side, reducing the
VSS lines, to the clock driver, adjacent to each other. This
maximum distance by a factor of 2.
tends to reduce the lines inductance and therefore the mag-
Using multilayer printed circuit boards with clock lines sand-
nitude of the voltage transients.
wiched between the VDD and VSS power plains minimizes
While discussing the clock driver, it should be pointed out
the inductance of the clock lines. It also serves the function
that the DS0026 is a relatively low input impedance device.
of preventing the clocks from coupling noise into input and
It is possible to couple current noise into the input without
output lines. Unfortunately multilayer printed circuit boards
seeing a significant voltage. Since the noise is difficult to
detect with an oscilloscope it is often overlooked.
www.national.com
6
Application Hints
This has been a hypothetical example to emphasize that
(Continued)
with 20V low rise/fall time transitions, parasitic elements can
Lastly, the clock lines must be considered as noise genera-
not be neglected. In this example, 1 pF of parasitic capaci-
tors. Figure 5 shows a clock coupled through a parasitic
tance could cause system malfunction, because a 7404
coupling capacitor, CC, to eight data input lines being driven
without a pull up resistor has typically only 0.3V of noise
by a 7404. A parasitic lumped line inductance, L, is also
margin in the "1" state at 25?C. Of course it is stretching
shown. Let us assume, for the sake of argument, that CC is
things to assume that the inductance, L, completely isolates
1 pF and that the rise time of the clock is high enough to
the clock transient from the 7404. However, it does point out
completely isolate the clock transient from the 7404 because
the need to minimize inductance in input/output as well as
of the inductance, L.
clock lines.
The output is current, so it is more meaningful to examine
the current that is coupled through a 1 pF parasitic capaci-
tance. The current would be:
This exceeds the total output current swing so it is obviously
significant.
Clock coupling to inputs and outputs can be minimized by
using multilayer printed circuit boards, as mentioned previ-
ously, physically isolating clock lines and/or running clock
00585320
lines at right angles to input/output lines. All of these tech-
niques tend to minimize parasitic coupling capacitance from
FIGURE 5. Clock Coupling
the clocks to the signals in question.
In considering clock coupling it is also important to have a
With a clock transition of 20V the magnitude of the voltage
detailed knowledge of the functional characteristics of the
generated across CL is:
device being used. As an example, for the MM5262, cou-
pling noise from the φ2 clock to the address lines is of no
particular consequence. On the other hand the address
inputs will be sensitive to noise coupled from φ1 clock.
7
www.national.com
Physical Dimensions
inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package (N)
Order Number DS0026CN
NS Package Number N08E
8-Lead Small Outline Molded package (M)
NS Package Number M08A
www.national.com
8
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
8-Lead Mini SOIC Package (MM)
NS Package Number MU08A
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component is any component of a life
1. Life support devices or systems are devices or
support device or system whose failure to perform
systems which, (a) are intended for surgical implant
can be reasonably expected to cause the failure of
into the body, or (b) support or sustain life, and
the life support device or system, or to affect its
whose failure to perform when properly used in
safety or effectiveness.
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
National Semiconductor
National Semiconductor
National Semiconductor
Corporation
Europe
Asia Pacific Customer
Japan Ltd.
Americas
Fax: +49 (0) 180-530 85 86
Response Group
Tel: 81-3-5639-7560
Email: support@nsc.com
Email: europe.support@nsc.com
Tel: 65-2544466
Fax: 81-3-5639-7507
Deutsch Tel: +49 (0) 69 9508 6208
Fax: 65-2504466
English  Tel: +44 (0) 870 24 0 2171
Email: ap.support@nsc.com
Fran?s Tel: +33 (0) 1 41 91 8790
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.