Ij

Complete, High Speed
16-Bit A/D Converters
AD1376/AD1377
For the AD1376, the serial output function is nonfunc-
FEATURES
tional after date code 0111. For the AD1377, the serial
Complete 16-Bit Converters with Reference and Clock
0.003% Maximum Nonlinearity
output function is nonfunctional after date code 0210. The
user option of applying external clock on the CONVERT
No Missing Codes to 14 Bits over Temperature
START pin to slow down the internally set conversion time
Fast Conversion
17  s to 16 Bits (AD1376)
is no longer available for either part.
10  s to 16 Bits (AD1377)
Short Cycle Capability
PRODUCT HIGHLIGHTS
1. The AD1376/AD1377 provides 16-bit resolution with a
Parallel Outputs
maximum linearity error of ? 0.003% (1/2 LSB14) at
Low Power
25?C.
645 mW Typical (AD1376)
2. AD1376 conversion time is 14 ?s (typical) short
585 mW Typical (AD1377)
cycled to 14 bits, and 16 ?s to 16 bits.
Industry-Standard Pinout
3. AD1377 conversion time is 8 ?s (typical) short cycled
GENERAL DESCRIPTION
to 14 bits, and 9 ?s to 16 bits.
The AD1376/AD1377 are high resolution, 16-bit analog-to-
4. Two binary codes are available on the digital output.
digital converters with internal reference, clock, and
They are CSB (complementary straight binary) for
laser-trimmed thin-film applications resistors. They are
unipolar input voltage ranges and COB (complementary
packaged in compact 32-lead, ceramic seam sealed (her-
offset binary) for bipolar input ranges. Complementary
metic), dual-in-line packages (DIP). Thin-film scaling
twos complement (CTC) coding may be obtained by
resistors provide bipolar input ranges of ? 2.5 V, ? 5 V, ? 10 V
inverting Pin 1 (MSB).
and unipolar input ranges of 0 V to +5 V, 0 V to +10 V, and
5. The AD1376 and AD1377 include internal reference
0 V to +20 V.
and clock, with external clock rate adjust pin, and paral-
Digital output data is provided in parallel form with corre-
lel digital outputs.
sponding clock and status outputs. All digital inputs and
outputs are TTL compatible.
FUNCTIONAL BLOCK DIAGRAM
SERIAL OUT (NOT SUPPORTED)
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise
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www.analog.com
under any patent or patent rights of Analog Devices. Trademarks and
Fax: 781/326-8703
? 2003 Analog Devices, Inc. All rights reserved.
registered trademarks are the property of their respective companies.
AD1376/AD1377?SPECIFICATIONS
(typical at TA = 25 C, VS =
15 V, +5 V, unless otherwise noted.)
Model
AD1376JD/AD1377JD
AD1376KD/AD1377KD
Unit
RESOLUTION
16 (max)
16 (max)
Bits
ANALOG INPUTS
Voltage Ranges
? 2.5, ? 5, ? 10
? 2.5, ? 5, ? 10
Bipolar
V
Unipolar
0 to +5, 0 to +10, 0 to +20
0 to +5, 0 to +10, 0 to +20
V
Impedance (Direct Input)
0 V to +5 V, ? 2.5 V
k
1.88
1.88
0 V to +10 V, ? 5.0 V
k
3.75
3.75
0 V to +20 V, ? 10 V
k
7.50
7.50
DIGITAL INPUTS1
Convert Command
Positive Pulse 50 ns Wide (min) Trailing Edge Initiates Conversion
Logic Loading
1
1
LS TTL Load
TRANSFER CHARACTERISTICS2
ACCURACY
? 0.053 (? 0.2 max)
? 0.053 (? 0.2 max)
%
Gain Error
Offset Error
? 0.053 (? 0.1 max)
? 0.053 (? 0.1 max)
% of FSR4
Unipolar
? 0.053 (? 0.2 max)
? 0.053 (? 0.2 max)
Bipolar
% of FSR
? 0.006
? 0.003
Linearity Error (Max)
% of FSR
? 1/2
? 1/2
Inherent Quantization Error
LSB
? 0.003
? 0.003
Differential Linearity Error
% of FSR
POWER SUPPLY SENSITIVITY
? 15 V DC (? 0.75 V)
% of FSR/% VS
0.0015
0.0015
+5 V DC (? 0.25 V)
% of FSR/% VS
0.001
0.001
CONVERSION TIME5
?s
12 Bits (AD1376)
11.5 (13 max)
11.5 (13 max)
?s
14 Bits (AD1376)
13.5 (15 max)
13.5 (15 max)
?s
16 Bits (AD1376)
15.5 (17 max)
15.5 (17 max)
?s
14 Bits (AD1377)
8.75 max
8.75 max
?s
16 Bits (AD1377)
10 max
10 max
POWER SUPPLY REQUIREMENTS
? 15, ? 0.5 (max)
? 15, ? 0.5 (max)
Rated Voltage, Analog
V dc
+5, ? 0.25 (max)
+5, ? 0.25 (max)
Rated Voltage, Digital
V dc
AD1376 Power Consumption
645 (850 max)
645 (850 max)
mW
+15 V Supply Drain
+16
+16
mA
?15 V Supply Drain
?21
?21
mA
+5 V Supply Drain
+18
+18
mA
AD1377 Power Consumption
600 (800 max)
600 (800 max)
mW
+15 V Supply Drain
+10
+10
mA
?15 V Supply Drain
?23
?23
mA
+5 V Supply Drain
+18
+18
mA
WARM-UP TIME
1
1
minutes
DRIFT6
? 15 (max)
? 5 (? 15 max)
ppm/?C
Gain
Offset
? 2 (? 4 max)
? 2 (? 4 max)
ppm of FSR/?C
Unipolar
? 10 (max)
? 3 (? 10 max)
ppm of FSR/?C
Bipolar
? 2 (? 3 max)
? 0.3 (? 2 max)
ppm of FSR/?C
Linearity
Guaranteed No Missing Code
?C
Temperature Range
0 to 70 (13 Bits)
0 to 70 (14 Bits)
?2?
REV. C
AD1376/AD1377
Model
AD1376JD/AD1377JD
AD1376KD/AD1377KD
Unit
DIGITAL OUTPUT1
(All Codes Complementary)
Parallel
Output Codes7
Unipolar
CSB
CSB
COB, CTC8
COB, CTC8
Bipolar
Output Drive
5
5
LSTTL Loads
Status
Logic 1 during Conversion
Status Output Drive
5 (max)
5 (max)
LSTTL Loads
Internal Clock9
Clock Output Drive
5 (max)
5 (max)
LSTTL Loads
Frequency
1040/1750
1040/1750
kHz
TEMPERATURE RANGE
?C
Specification
0 to 70
0 to 70
?C
Operating
?25 to +85
?25 to +85
?C
Storage
?55 to +125
?55 to +125
NOTES
1
Logic 0 = 0.8 V, max. Logic 1 = 2.0 V, min for inputs. For digital outputs Logic 0 = 0.4 V max. Logic 1 = 2.4 V min.
Tested on ? 10 V and 0 V to +10 V ranges.
2
3
Adjustable to zero.
4
Full-scale range.
5
Guaranteed but not 100% production tested.
6
Conversion time may be shortened with "short cycle" set for lower resolution.
7
CSB?Complementary Straight Binary. COB?Complementary Offset Binary. CTC?Complementary Twos Complement.
8
CTC coding obtained by inverting MSB (Pin 1).
9
With Pin 23, clock rate controls tied to digital ground.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? 18 V
Maximum Conversion
Logic Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Temperature Linearity  Time
Package
Analog Inputs (Pins 24 and 25) . . . . . . . . . . . . . . . . . . . ? 25 V
Option*
Model
Range
Error
(16 Bits)
Analog Ground to Digital Ground . . . . . . . . . . . . . . . . . ? 0.3 V
0?C to 70?C
? 0.006%
17 ?s
AD1376JD
DH-32E
Digital Inputs . . . . . . . . . . . . . . . . . . . . ?0.3 V to VDD + 0.3 V
0?C to 70?C
? 0.003%
17 ?s
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175?C
AD1376KD
DH-32E
0?C to 70?C
? 0.006%
10 ?s
Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15?C
AD1377JD
DH-32E
0?C to 70?C
? 0.003%
10 ?s
AD1377KD
DH-32E
Lead Temperature (10 sec) . . . . . . . . . . . . . . . . . . . . . . 300?C
*DH-32E = Ceramic DIP.
*Absolute maximum ratings are limiting values to be applied individually, and
beyond which the service ability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD1376/AD1377 feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. C
?3?
AD1376/AD1377
APPLICATIONS
The AD1376/AD1377 are excellent for use in high resolution
applications requiring moderate speed and high accuracy or
stability over commercial (0?C to 70?C) temperature ranges (for
extended temperature ranges, the pin compatible AD1378 is
recommended.) Typical applications include medical and ana-
lytic instrumentation, precision measurement for industrial
robotics, automatic test equipment (ATE), multichannel data
acquisition systems, servo control systems, or anywhere wide
dynamic range is required. A proprietary monolithic DAC
and laser-trimmed thin-film resistors guarantee a maximum
nonlinearity of ? 0.003% (1/2 LSB14). The converters may be
short cycled to achieve faster conversion times--15 ?s to 14 bits
for the AD1376 or 8 ?s to 14 bits for the AD1377.
DESCRIPTION OF OPERATION
On receipt of a CONVERT START command, the AD1376/
AD1377 converts the voltage at its analog input into an equiva-
Figure 1. Linearity Error vs. Temperature
lent 16-bit binary number. This conversion is accomplished as
follows: the 16-bit successive approximation register (SAR) has
its 16-bit outputs connected both to the device bit output pins
and to the corresponding bit inputs of the feedback DAC. The
analog input is successively compared to the feedback DAC
output, one hit at a time (MSB first, LSB last). The decision to
keep or reject each bit is then made at the completion of each
bit comparison period, depending on the state of the compara-
tor at that time.
GAIN ADJUSTMENT
The gain adjust circuit consists of a 100 ppm/?C potentiometer
connected across ? VS with its slider connected through a 300 k
resistor to the gain adjust Pin 29 as shown in Figure 4.
If no external trim adjustment is desired, Pin 27 (OFFSET
ADJ) and Pin 29 (GAIN ADJ) may be left open.
Figure 2. AD1376 Nonlinearity vs. Conversion Time
Figure 4. Gain Adjustment Circuit (?0.2% FSR)
OFFSET ADJUSTMENT
The zero adjust circuit consists of a 100 ppm/?C potentiometer
connected across ? VS with its slider connected through a 1.8 M
resistor to Comparator Input Pin 27 for all ranges. As shown
in Figure 5, the tolerance of this fixed resistor is not critical,
and a carbon composition type is generally adequate. Using a
carbon composition resistor having a ?1200 ppm/?C tempera-
ture coefficent contributes a worst-case offset temperature
coefficent of 32 LSB14   61 ppm/LSB14   1200 ppm/?C =
2.3 ppm/?C of FSR, if the OFFSET ADJ potentiometer is set
at either end of its adjustment range. Since the maximum offset
adjustment required is typically no more than ? 16 LSB14, use of
Figure 3. Gain Drift Error vs. Temperature
a carbon composition offset summing resistor typically con-
tributes no more than 1 ppm/?C of FSR offset temperature
coefficent.
?4?
REV. C
AD1376/AD1377
Figure 5. Offset Adjustment Circuit (?0.3% FSR)
An alternate offset adjust circuit, which contributes negligible
offset temperature coefficent if metal film resistors (tempera-
ture coefficent <100 ppm/?C) are used, is shown in Figure 6.
Figure 6. Low Temperature Coefficent Zero Adjustment
Circuit
Figure 7. Timing Diagram (Binary Code
In either adjust circuit, the fixed resistor connected to Pin 27
0110011101111010)
should be located close to this pin to keep the pin connection
short. Comparator Input Pin 27 is quite sensitive to external
DIGITAL OUTPUT DATA
noise pickup and should be guarded by analog common.
Parallel data from TTL storage registers is in negative true form
(Logic 1 = 0 V and Logic 0 = 2.4 V). Parallel data output coding is
TIMING
complementary binary for unipolar ranges and complementary
The timing diagram is shown in Figure 7. Receipt of a CONVERT
offset binary for bipolar ranges. Parallel data becomes valid at
START signal sets the STATUS flag, indicating conversion in
least 20 ns before the STATUS flag returns to Logic 0, permit-
progress. This, in turn, removes the inhibit applied to the gated
ting parallel data transfer to be clocked on the 1 to 0 transition
clock, permitting it to run through 17 cycles. All the SAR paral-
of the STATUS flag (see Figure 8).
lel bits, the STATUS flip-flops, and the gated clock inhibit signal
are initialized on the trailing edge of the CONVERT START
signal. At time t0, B1 is reset and B2?B16 are set unconditionally.
At t1, the Bit 1 decision is made (keep) and Bit 2 is reset uncon-
ditionally. This sequence continues until the Bit 16 (LSB) decision
(keep) is made at t16. The STATUS flag is reset, indicating that
the conversion is complete and that the parallel output data is
valid. Resetting the STATUS flag restores the gated clock inhibit
signal, forcing the clock output to the low Logic 0 state. Note
Figure 8. LSB Valid to Status Low
that the clock remains low until the next conversion.
Corresponding parallel data bits become valid on the same
positive going clock edge.
REV. C
?5?
AD1376/AD1377
Table I. Short Cycle Connections
Resolution
Maximum Conversion
Maximum Conversion
Connect Short Cycle
Time? s (AD1377)
Time? s (AD1376)
Bits
(% FSR)
Status Flag Reset
Pin 32 to Pin
NC (Open)
16
0.0015
10
17.1
t16
15
0.003
9.4
16.1
t15
16
15
14
0.006
8.7
15.0
t14
14
13
0.012
8.1
13.9
t13
13
12
0.024
7.5
12.9
t12
10
0.100
6.3
10.7
t10
11
8
0.390
5.0
8.6
t8
9
Table II. Input Scaling Connections
Short Cycle Input
A short cycle input, Pin 32, permits the timing cycle shown in
Input
Connect
Connect
Connect
Figure 7 to be terminated after any number of desired bits has
Signal
Output
Pin 26
Pin 24
Input
been converted, permitting somewhat shorter conversion times
Line
Code
to Pin
to
Signal to
in applications not requiring full 16-bit resolution. When 10-bit
? 10 V
resolution is desired, Pin 32 is connected to Bit 11 output Pin 11.
COB
27
Input
24
The conversion cycle then terminates and the STATUS flag
Signal
?5 V
resets after the Bit 10 decision (timing diagram of Figure 7).
COB
27
Open
25
? 2.5 V
Short cycle connections and associated 8-, 10-, 12-, 13-, 14-,
COB
27
Pin 27
25
and 15-bit conversion times are summarized in Table I, for a
0 V to +5 V
CSB
22
Pin 27
25
1.6 MHz clock (AD1377) or 933 kHz (AD1376).
0 V to +10 V
CSB
22
Open
25
0 V to +20 V
CSB
22
Input
24
INPUT SCALING
Signal
The ADC inputs should be scaled as close to the maximum input
Pin 27 is extremely sensitive to noise and should be guarded by analog com-
signal range as possible in order to use the maximum signal
mon.
resolution of the ADC. Connect the input signal as shown in
Table II. See Figure 9 for circuit details.
Figure 9. Input Scaling Circuit
?6?
REV. C
AD1376/AD1377
Table III. Transition Values vs. Calibration Codes
Code Under Test
Low-Side Transition Values
? 10 V
?5 V
? 2.5 V
MSB
LSB
Range
0 V to +10 V
0 V to +5 V
000 ......... 000*
+Full Scale
+10 V
+5 V
+2.5 V
+10 V
+5 V
?3/2 LS
?3/2 LSB
?3/2 LSB
?3/2 LSB
?3/2 LSB
011 ......... 111
Midscale
0?1/2 LSB
0?1/2 LSB
0?1/2 LSB
+5 V?1/2 LSB
+2.5 V?1/2 LSB
111 ......... 110
?Full Scale
?10 V
?5 V
?2.5 V
0V
0V
+1/2 LSB
+1/2 LSB
+1/2 LSB
+1/2 LSB
+1/2 LSB
*Voltages given are the nominal value for transition to the code specified.
Note: For LSB value for range and resolution used, see Table IV.
Table IV. Input Voltage Range and LSB Values
Analog Input
? 10 V
?5 V
? 2.5 V
Voltage Range
0 V to +10 V
0 V to +5 V
COB1
COB1
COB1
Code
or CTC2
or CTC2
or CTC2
CSB3
CSB3
Designation
One Least
FSR
20 V
10 V
5V
10 V
5V
2n
2n
2n
2n
2n
2n
Significant
Bit (LSB)
n=8
78.13 mV
39.06 mV
19.53 mV
39.06 mV
19.53 mV
n = 10
19.53 mV
9.77 mV
4.88 mV
9.77 mV
4.88 mV
n = 12
4.88 mV
2.44 mV
1.22 mV
2.44 mV
1.22 mV
n = 13
2.44 mV
1.22 mV
0.61 mV
1.22 mV
0.61 mV
n = 14
1.22 mV
0.61 mV
0.31 mV
0.61 mV
0.31 mV
n = 15
0.61 mV
0.31 mV
0.15 mV
0.31 mV
0.15 mV
NOTES
1
COB = Complementary Offset Binary.
CTC = Complementary Twos Complementary--achieved by using an inverter to complement the most significant bit to product (MSB).
2
3
CSB = Complementary Straight Binary.
REV. C
?7?
AD1376/AD1377
CALIBRATION
(14-Bit Resolution Examples)
External ZERO ADJ and GAIN ADJ potentiometers, connected
as shown in Figures 4 and 5, are used for device calibration. To
prevent interaction of these two adjustments, zero is always
adjusted first and then gain. Zero is adjusted with the analog
input near the most negative end of the analog range (0 for unipo-
lar and ?FS for bipolar input ranges). Gain is adjusted with the
analog input near the most positive end of the analog range.
0 V to 10 V Range
Set analog input to +1 LSB14 = 0.00061 V. Adjust zero for
digital output = 11111111111110.
Zero is now calibrated. Set analog input to +FSR ? 2 LSB =
9.99878 V. Adjust gain for 00000000000001 digital output
code; full scale (gain) is now calibrated. Half-scale calibration
Figure 11. Analog and Power Connections for
check: set analog input to 5.00000 V; digital output code should
Bipolar ?10 V to +10 V Input Range
be 01111111111111.
Other Ranges
Representative digital coding for 0 V to +10 V and ?10 V to
?10 V to +10 V Range
Set analog input to 9.99878 V; adjust zero for 1111111111110
+10 V ranges is given above. Coding relationships and calibra-
digital output (complementary offset binary) code. Set analog
tion points for 0 V to +5 V, ?2.5 V to +2.5 V, and ?5 V to +5 V
input to 9.99756 V; adjust gain for 00000000000001 digital out-
ranges can be found by halving proportionally the correspond-
put (complementary offset binary) code. Half-scale calibration
ing code equivalents listed for the 0 V to +10 V and ?10 V to
check-set analog input to 0.00000 V; digital output (comple-
+10 V ranges, respectively, as indicated in Table III.
mentary offset binary) code should be 01111111111111.
Zero- and full-scale calibration can be accomplished to a preci-
sion of approximately ? 1/2 LSB using the static adjustment
procedure described previously. By summing a small sine or
triangular wave voltage with the signal applied to the analog
input, the output can be cycled through each of the calibration
codes of interest to more accurately determine the center (or
end points) of each discrete quantization level. A detailed
description of this dynamic calibration technique is presented in
Analog-Digital Conversion Handbook, edited by D. H. Sheingold,
Prentice Hall, Inc., 1986.
GROUNDING, DECOUPLING, AND LAYOUT
CONSIDERATIONS
Many data acquisition components have two or more ground
pins that are not connected together within the device. These
grounds are usually referred to as the logic power return,
analog common (analog power return), and analog signal
Figure 10. Analog and Power Connections for
ground. These grounds (Pins 19 and 22) must be tied together
Unipolar 0 V to 10 V Input Range
at one point for the ADC as close as possible to the converter.
?8?
REV. C
AD1376/AD1377
Ideally, a single solid analog ground plane under the converter
would be desirable. Current flows through the wires and etch
stripes of the circuit cards, and since these paths have resistance
and inductance, hundreds of millivolts can be generated between
the system analog ground point and the ground pins of the
ADC. Separate wide conductor stripe ground returns should be
provided for high resolution converters to minimize noise and
IR losses from the current flow in the path from the converter to
the system ground point. In this way, ADC supply currents and
other digital logic-gate return currents are not summed into the
same return path as analog signals where they would cause
measurement errors.
Each of the ADC supply terminals should be capacitively
decoupled as close to the ADC as possible. A large value
capacitor such as 1 ?F in parallel with a 0.1 ?F capacitor is
usually sufficient. Analog supplies are to be bypassed to the
Figure 13. Basic Data Acquisition System
analog power return pin and the logic supply is bypassed to the
Interconnections
logic power return pin.
A much safer approach is to add a flip-flop, as shown in Figure 14.
The metal cover is internally grounded with respect to the
The rising edge of CONVERT START places the track-and-
power supplies, grounds, and electrical signals. Do not exter-
hold device into hold mode before the ADC reset transients
nally ground the cover.
begin. The falling edge of STATUS places the AD386 back
into track mode. System throughput will be reduced if a long
CLOCK RATE CONTROL
CONVERT START pulse is used. Throughput can be calcu-
The AD1376/AD1377 may be operated at faster conversion
lated from
times by connecting the clock rate control (Pin 23) to an
external multiturn trim potentiometer (TCR <100 ppm/?C) as
1
Throughput =
TACQ + TCONV + TCS
shown in Figure 12.
where TACQ is the track-and-hold acquisition time, TCONV is the
time required for the ADC conversion, and TCS is the duration
of CONVERT START. The combination of the AD1376 and
AD386 will provide greater than 50 kHz throughput. No signifi-
cant track-and-hold droop error will be introduced, provided
Figure 12. Clock Rate Control Circuit
the width of CONVERT START is small compared with the
ADC's conversion time.
HIGH RESOLUTION DATA ACQUISITION SYSTEM
The essential details of a high resolution data acquisition
system using the AD386 and AD1376 or AD1377 are shown
in Figure 13. Conversion is initiated by the falling edge of the
CONVERT START pulse. This edge drives the AD1376's or
AD1377's STATUS line high. The inverter then drives the
AD386 into hold mode. STATUS remains high throughout the
conversion and returns low once the conversion is completed.
This allows the AD386 to re-enter track mode.
This circuit can exhibit nonlinearities arising from transients
produced at the ADC's input by the falling edge of CONVERT
START. This edge resets the ADC's internal DAC; the result-
ing transient depends on the SHA's present output voltage and
the ADC's prior conversion result. In the circuit of Figure 14,
the falling edge of CONVERT START also places the SHA
into hold mode (via the ADC's STATUS output), causing the
reset transient to occur at the same moment as the SHA's track-
and-hold transition. Timing skews and capacitive coupling can
cause some of the transient signal to add to the signal being
acquired by the SHA, introducing nonlinearity.
Figure 14. Improved Data Acquisition System
REV. C
?9?
AD1376/AD1377
OUTLINE DIMENSIONS
32-Lead Bottom-Brazed Ceramic DIP [BBCDIP/H]
(DH-32E)
Dimensions shown in inches and (millimeters)
1.750 (44.45) MAX
17
32
1.105 (28.07)
1.075 (27.31)
16
1
0.035 (0.89)
PIN 1
INDICATOR
0.225 (5.72)
0.015 (0.38)
MAX
0.180 (4.57)
0.015 (0.38)
MIN
0.008 (0.20)
0.145 (3.68)
0.910 (23.11)
MIN
0.120 (3.05)
0.890 (22.61)
MAX
0.100 (2.54)
0.023 (0.58)
0.070 (1.78)
BSC
0.014 (0.36)
0.030 (0.76)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
?10?
REV. C
AD1376/AD1377
Revision History
Location
Page
6/03--Data Sheet changed from REV. B to REV. C.
Removed serial output function and adjustable clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal
Updated format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Inserted ESD WARNING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Change to Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Deleted text from DIGITAL OUTPUT DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Deleted Figure 9 and renumbered remainder of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Deleted the Using the AD1376 or AD1377 at Slower Conversion Times section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Deleted Figure 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Change to Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Change to Figure 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
REV. C
?11?
?12?