Ij

a
Parallel-Port 16-Bit
?
SoundPort Stereo Codec
AD1845
FEATURES
plete on-chip filtering, MPC Level-2 compliant analog mixing,
Single-Chip Integrated ∑∆ Digital Audio Stereo Codec
programmable gain, attenuation and mute, a variable sample
Microsoft? and Windows? Sound System Compatible
frequency generator, FIFOs, and supports advanced power-
MPC Level-2+ Compliant Mixing
down modes. It provides a direct, byte-wide interface to both
16 mA Bus Drive Capability
ISA ("AT") and EISA computer buses for simplified implemen-
Supports Two DMA Channels for Full Duplex Operation
tation on a computer motherboard or add-in card.
On-Chip Capture and Playback FIFOs
The AD1845 SoundPort Stereo Codec supports a DMA re-
Advanced Power-Down Modes
quest/grant architecture for transferring data with the host com-
Programmable Gain and Attenuation
puter bus. One or two DMA channels can be supported.
Sample Rates from 4.0 kHz to 50 kHz Derived from a
Programmed I/O (PIO) mode is also supported for control
Single Clock or Crystal Input
register accesses and for applications lacking DMA control.
68-Lead PLCC, 100-Lead TQFP Packages
Two input control lines support mixed direct and indirect ad-
Operation from +5 V Supplies
dressing of thirty-seven internal control registers over this asyn-
Byte-Wide Parallel Interface to ISA and EISA Buses
chronous interface. The AD1845 includes dual DMA count
Pin Compatible with AD1848, AD1846, CS4248, CS4231
registers for full duplex operation enabling the AD1845 to cap-
ture data on one DMA channel and play back data on a separate
channel. The FIFOs on the AD1845 reduce the risk of losing
data when making DMA transfers over the ISA/EISA bus. The
PRODUCT OVERVIEW
FIFOs buffer data transfers and allow for relaxed timing in
The Parallel Port AD1845 SoundPort Stereo Codec integrates
acknowledging requests for capture and playback data.
key audio data conversion and control functions into a single
integrated circuit. The AD1845 provides a complete, single chip
computer audio solution for business audio and multimedia
(Continued on Page 9)
applications. The codec includes stereo audio converters, com-
FUNCTIONAL BLOCK DIAGRAM
ANALOG
POWER DOWN
RESET
DIGITAL
ANALOG SUPPLY
DIGITAL SUPPLY
CLOCK SOURCE
L_MIC
0 dB/
AD1845
VARIABLE SAMPLE
20 dB
PLAYBACK REQ
R_MIC
FREQUENCY GENERATOR
L_LINE
L
PLAYBACK ACK
A/D
GAIN
R_LINE
CONVERTER
-LAW
U
CAPTURE REQ
L_AUX1
X
A-LAW
FIFO
R
A/D
CAPTURE ACK
LINEAR
R_AUX1
GAIN
P
CONVERTER
A
ADR1:0
R
A
DATA7:0
L
DIGITAL MIX
GAM = GAIN
GAM
GAM
GAM
L
CS
ATTENUATE
ATTENTUATE
E
MUTE
L
RD
L ATTENUATE
D/A
M MUTE
P
L_OUT
CONVERTER
WR
-LAW
O
R
A-LAW
BUS DRIVER
FIFO
MUTE
M_OUT
T
CONTROL
LINEAR
R
D/A
ATTENUATE
HOST DMA
R_OUT
CONVERTER
MUTE
INTERRUPT
EXTERNAL
GAM
GAM
M_IN
CONTROL
L_AUX2
REFERENCE
R_AUX2
CONTROL
REGISTERS
VREF_F
VREF
SoundPort is a registered trademark of Analog Devices, Inc.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A
use, nor for any infringements of patents or other rights of third parties
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
which may result from its use. No license is granted by implication or
Fax: 781/326-8703
? Analog Devices, Inc., 1997
otherwise under any patent or patent rights of Analog Devices.
AD1845?SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
?C
DAC Test Conditions
Temperature
25
Calibrated
Digital Supply (VDD)
5.0
V
0 dB Relative to Full Scale
Analog Supply (VCC)
5.0
V
16-Bit Linear Mode
Word Rate (FS)
48
kHz
10 kOutput Load
Input Signal
1008
Hz
Mute Off, OL = 0
Analog Output Passband
20 Hz to 20 kHz
ADC Test Conditions
ADC FFT Size
2048
Calibrated
DAC FFT Size
8192
0 dB Gain
VIH
5
V
?1.0 dB Relative to Full Scale
VIL
0
V
Line Input
16-Bit Linear Mode
ANALOG INPUT
Min
Typ
Max
Units
Input Voltage (RMS Values Assume Sine Wave Input)
Line
1
V rms
2.55
2.83
3.35
V p-p
MIC with +20 dB Gain (MGE = 1)
0.1
V rms
0.255
0.283
0.335
V p-p
MIC with 0 dB Gain (MGE = 0)
1
V rms
2.55
2.83
3.35
V p-p
k
Input Impedance*
10
17
Input Capacitance
15
pF
PROGRAMMABLE GAIN AMPLIFIER?ADC
Min
Typ
Max
Units
Step Size (All Steps Tested)
(0 dB to 22.5 dB)
0.7
1.5
1.9
dB
PGA Gain Range Span
21.5
22.5
23.5
dB
AUXILIARY LINE, MONO, AND MICROPHONE INPUT ANALOG GAIN/AMPLIFIERS/ATTENUATORS
Min
Typ
Max
Units
Step Size : AUX1, AUX2, LINE, MIC (All Steps Tested)
(+12 dB to ?30 dB)
1.25
1.5
1.75
dB
(?31.5 dB to ?34.5 dB)
1
1.5
2.0
dB
Step Size: M_IN (All Steps Tested)
(0 dB to ?39 dB)
2.5
3.0
3.6
dB
(?42 dB to ?45 dB)
2.2
3.0
3.85
dB
Input Gain/Attenuation Range: AUX1, AUX2, LINE, MIC
45.0
46.5
49.0
dB
Input Gain/Attenuation Range: M_IN
42
45
49
dB
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
Min
Max
Units
0.4 ?FS
Hz
Passband
0
? 0.1
Passband Ripple
dB
0.4 ?FS
0.6 ?FS
Transition Band
Hz
0.6 ?FS
Stopband
Hz
Stopband Rejection
74
dB
Group Delay
15/FS
?s
Group Delay Variation Over Passband
0.0
*Guaranteed, not tested.
?2?
REV. C
AD1845
ANALOG-TO-DIGITAL CONVERTERS
Min
Typ
Max
Units
Resolution
16
Bits
Dynamic Range (?60 dB Input, THD+N Referenced to Full Scale, A-Weighted)
73
81
dB
THD+N (Referenced to Full Scale)
0.025
%
?76
?72
dB
Signal-to-Intermodulation Distortion
85
dB
ADC Crosstalk*
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
?90
?80
dB
Line to MIC (Input LINE, Ground and Select MIC, Read ADC)
?90
?80
dB
Line to AUX1
?90
?80
dB
Line to AUX2
?90
?80
dB
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
?18.5
+10
%
? 0.9
Interchannel Gain Mismatch (Difference of Gain Errors)
dB
ADC Offset Error
10
mV
DIGITAL-TO-ANALOG CONVERTERS
Min
Typ
Max
Units
Resolution
16
Bits
Dynamic Range (?60 dB Input, THD+N Referenced to Full Scale, A-Weighted)
74
82
dB
THD+N (Referenced to Full Scale)
0.032
%
?78
?70
dB
Signal-to-Intermodulation Distortion
90
dB
Gain Error (Full-Scale Span Relative to Nominal Output Voltage)
?14.5
+10
%
? 0.6
Interchannel Gain Mismatch (Difference of Gain Errors)
dB
DAC Crosstalk* (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT)
?80
dB
Total Out-of-Band Energy (Measured from 0.6 ?FS to 100 kHz)*
?50
dB
Audible Out-of-Band Energy (Measured from 0.6 ?FS to 20 kHz)*
?70
dB
DAC ATTENUATOR
Min
Typ
Max
Units
Step Size (0 dB to ?22.5 dB)
1.3
1.5
1.7
dB
Step Size (?22.5 dB to ?94.5 dB)*
1.0
1.5
2.0
dB
Output Attenuation Range Span*
93.5
94.5
95.5
dB
ANALOG OUTPUT
Min
Typ
Max
Units
Full-Scale Output Voltage
OL = 0
1.7
2.0
2.2
V p-p
OL = 1
2.4
2.83
3.11
V p-p
Output Impedance*
600
k
External Load Impedance
10
Output Capacitance*
15
pF
External Load Capacitance
100
pF
VREF
2.05
2.25
2.60
V
?A
VREF Current Drive
100
k
VREF Output Impedance
4
Mute Attenuation of 0 dB Fundamental* (L_OUT, R_OUT, M_OUT)
?80
dB
?5
Mute Click (Muted Output Minus Unmuted Midscale DAC Output)*
mV
*Guaranteed, not tested.
REV. C
?3?
AD1845
SYSTEM SPECIFICATIONS
Min
Typ
Max
Units
System Frequency Response Ripple (Line In to Line Out)*
1.0
dB
?1
Differential Nonlinearity*
LSB
Phase Linearity Deviation*
5
Degrees
STATIC DIGITAL SPECIFICATIONS
Min
Max
Units
High Level Input Voltage (VIH)
Digital Inputs
2.4
V
XTAL1I
2.4
V
Low Level Input Voltage (VIL)
0.8
V
High Level Output Voltage (VOH) IOH = ?2 mA
2.4
V
Low Level Output Voltage (VOL) IOL = 2 mA
0.4
V
?A
Input Leakage Current
?10
10
?A
Output Leakage Current
?10
10
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE, V  DD = VCC = 5.0 V)
Min
Max
Units
WR/RD Strobe Width
(tSTW)
100
ns
WR/RD Rising to WR/RD Falling
(tBWND)
80
ns
Write Data Setup to WR Rising
(tWDSU)
10
ns
RD Falling to Valid Read Data
(tRDDV)
40
ns
CS Setup to WR/RD Falling
(tCSSU)
10
ns
CS Hold from WR/RD Rising
(tCSHD)
0
ns
Adr Setup to WR/RD Falling
(tADSU)
10
ns
Adr Hold from WR/RD Rising
(tADHD)
10
ns
DAK Rising to WR/RD Falling
(tSUDK1)
20
ns
DAK Falling to WR/RD Rising
(tSUDK2)
0
ns
DAK Setup to WR/RD Falling
(tDKSU)
10
ns
Data Hold from RD Rising
(tDHD1)
20
ns
Data Hold from WR Rising
(tDHD2)
15
ns
DRQ Hold from WR/RD Falling
(tDRHD)
25
ns
DAK Hold from WR Rising
(tDKHDa)
10
ns
10
ns
DAK Hold from RD Rising
(tDKHDb)
DBEN/DBDIR Delay from WR/RD Falling
30
ns
(tDBDL)
300
ns
PWRDWN and RESET Low Pulsewidth
*Guaranteed, not tested.
REV. C
?4?
AD1845
POWER SUPPLY
Min
Typ
Max
Units
Power Supply Range?Digital and Analog
4.75
5.25
V
Power Supply Current
130
mA
Analog Supply Current
45
mA
Digital Supply Current
85
mA
Power Dissipation
(Current ?Nominal Supplies)
650
mW
Power-Down Supply Current
2
mA
Reset Supply Current
2
mA
Total Power-Down Supply Current
30
mA
Standby Supply Current
36
mA
Mixer Power-Down Supply Current
70
mA
Mixer Only Supply Current
52
mA
ADC Power-Down Supply Current
80
mA
DAC Power-Down Supply Current
85
mA
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*
(At Both Analog and Digital Supply Pins, both ADCs and DACs)
40
dB
CLOCK SPECIFICATIONS*
Min
Max
Units
Input Clock Frequency
33
MHz
Recommended Clock Duty Cycle
10
90
%
Power Up Initialization Time
512
ms
*Guaranteed, not tested.
Specifications subject to change without notice.
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*
Temperature
Package
Package
Min
Max
Units
Option1
Model
Range
Description
Power Supplies
0?C to +70?C
AD1845JP
68-Lead PLCC
P-68A
Digital (VDD)
?0.3
6.0
V
0?C to +70?C
AD1845JP-REEL2
68-Lead PLCC
P-68A
Analog (VCC)
?0.3
6.0
V
0?C to +70?C
AD1845JST
100-Lead TQFP
ST-100
Input Current
? 10.0
(Except Supply Pins)
mA
NOTES
Analog Input Voltage (Signal Pins)
?0.3
VCC +0.3
V
1
P = Plastic Leaded Chip Carrier; ST = Thin Quad Flatpack.
2
Digital Input Voltage (Signal Pins)
?0.3
VDD +0.3
V
13" Reel, multiples of 250 pcs.
?C
Ambient Temperature (Operating)
0
+70
?C
ENVIRONMENTAL CONDITIONS
Storage Temperature
?65
+150
Ambient Temperature Rating:
*Stresses greater than those listed under Absolute Maximum Ratings may cause
TAMB = TCASE ? (PD CA)
permanent damage to the device. This is a stress rating only; functional operation
TCASE = Case Temperature in ?C
of the device at these or any other conditions above those indicated in the
PD = Power Dissipation in W
operational section of this specification is not implied. Exposure to absolute
θCA = Thermal Resistance (Case-to-Ambient)
maximum rating conditions for extended periods may affect device reliability.
θJA = Thermal Resistance (Junction-to-Ambient)
θJC = Thermal Resistance (Junction-to-Case)
JA
JC
CA
Package
38?C/W
8?C/W
30?C/W
PLCC
44?C/W
8?C/W
93?C/W
TQFP
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
WARNING!
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1845 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.
REV. C
?5?
AD1845
PIN DESIGNATIONS
60 RD
ADR0
10
59 CS
CDAK
11
58 XCTL1
CDRQ
12
57 INT
PDAK
13
56 XCTL0
PDRQ
14
55 NC
VDD
15
68-Lead PLCC
54 VDD
AD1845
16
GNDD
53 GNDD
TOP VIEW
17
XTAL1I
(Not to Scale)
52 NC
18
XTAL1O
51 NC
19
VDD
50 NC
20
GNDD
49 NC
21
XTAL2I
48 NC
22
XTAL2O
47 M_OUT
23
PWRDWN
46 M_IN
24
RESET
45 VDD
25
GNDD
44 GNDD
26
R_FILT
NC = NO CONNECT
RD
75
ADR0
1
CS
74
NC
2
XCTL1
73
NC
3
INT
72
NC
4
XCTL0
71
NC
5
NC
70
CDAK
6
NC
69
CDRQ
7
VDD
68
PDAK
8
GNDD
67
PDRQ
9
NC
66
VDD 10
NC
65
GNDD 11
AD1845
NC
64
100-Lead TQFP
XTAL1I 12
NC
63
TOP VIEW
XTAL1O 13
NC
62
(Not to Scale)
VDD 14
NC
61
GNDD 15
NC
60
XTAL2I 16
NC
59
XTAL2O 17
NC
58
PWRDWN 18
M_OUT
57
RESET 19
M_IN
56
GNDD 20
VDD
55
NC 21
54
GNDD
NC 22
53
NC
NC 23
52
NC
NC 24
51
NC
R_FILT 25
NC = NO CONNECT
REV. C
?6?
AD1845
PIN FUNCTION DESCRIPTIONS
Parallel Interface
Pin Name
PLCC TQFP
I/O
Description
CDRQ
12
7
O
Capture Data Request. The assertion of this signal HI indicates that the codec has a cap-
tured audio sample from the ADC ready for transfer. This signal will remain asserted
until the internal capture FIFO is empty.
CDAK
Capture Data Acknowledge. The assertion of this active LO signal indicates that the RD
11
6
I
cycle occurring is a DMA read from the capture buffer.
PDRQ
14
9
O
Playback Data Request. The assertion of this signal HI indicates that the codec is ready
for more DAC playback data. The signal will remain asserted until the internal playback
FIFO is full.
PDAK
Playback Data Acknowledge. The assertion of this active LO signal indicates that the WR
13
8
I
cycle occurring is a DMA write to the playback buffer.
ADR1:0
9 & 10 100 & 1
I
Codec Addresses. These address pins are asserted by the codec interface logic during a
control register/PIO access. The state of these address lines determine which direct
register is accessed.
RD
60
75
I
Read Command Strobe. This active LO signal defines a read cycle from the codec. The
cycle may be a read from the control/PIO registers, or the cycles could be a read from
the codec's DMA sample registers.
WR
61
76
I
Write Command Strobe. This active LO signal indicates a write cycle to the codec. The
cycle may be a write to the control/PIO registers, or the cycle could be a write to the
codec's DMA sample registers.
CS
59
74
I
AD1845 Chip Select. The codec will not respond to any control/PIO cycle accesses
unless this active LO signal is LO. This signal is ignored during DMA transfers.
DATA7:0
3?6 &
84?87 & I/O
Data Bus. These pins transfer data and control information between the codec and
65?68
90?93
the host.
DBEN
63
78
O
Data Bus Enable. This pin enables the external bus drivers. This signal is normally HI.
For control register/PIO cycles,
DBEN = (WR or RD) and CS
For DMA cycles,
DBEN = (WR or RD) and (PDAK or CDAK).
DBDIR
62
77
O
Data Bus Direction. This pin controls the direction of the data bus transceiver. HI
enables writes from the host bus to the AD1845; LO enables reads from the AD1845 to
the host bus. This signal is normally HI.
For control register/PIO cycles,
DBDIR = RD and CS
For DMA cycles,
DBDIR = RD and (PDAK or CDAK).
REV. C
?7?
AD1845
Analog Signals
Pin Name
PLCC TQFP
I/O
Description
L_LINE
30
31
I
Left Line Input.
R_LINE
27
28
I
Right Line Input.
L_MIC
29
30
I
Left Microphone Input. This signal can be either line level or ?20 dB from line level
(using the on-chip 20 dB gain block).
R_MIC
28
29
I
Right Microphone Input. This signal can be either line level or ?20 dB from line level
(using the on-chip 20 dB gain block).
L_AUX1
39
45
I
Left Auxiliary #1 Line Input.
R_AUX1
42
48
I
Right Auxiliary #1 Line Input.
L_AUX2
38
44
I
Left Auxiliary #2 Line Input.
R_AUX2
43
49
I
Right Auxiliary #2 Line Input.
L_OUT
40
46
O
Left Line Output.
R_OUT
41
47
O
Right Line Output.
M_IN
46
56
I
Mono Input.
M_OUT
47
57
O
Mono Output.
Miscellaneous
Pin Name
PLCC TQFP
I/O
Description
XTAL1I
17
12
I
24.576 MHz Crystal #1 Input.
XTAL1O
18
13
O
24.576 MHz Crystal #1 Output.
XTAL2I
21
16
Not used on the AD1845.
XTAL2O
22
17
Not used on the AD1845.
PWRDWN
23
18
I
Power Down Signal. Active LO places the AD1845 in its lowest power consumption
mode. All sections of the AD1845, including the digital interface, are shut down and
consume minimal power.
INT
57
72
O
Host Interrupt Pin. A host interrupt is generated to notify the host that a specified
event has occurred.
XCTL1:0
58 & 56 73 & 71
O
External Control. These signals reflect the current status of register bits inside the
AD1845. They can be used for signaling or to control external logic.
RESET
24
19
I
Reset. Active LO resets all digital registers and filters, and resets all analog filters. Active
LO places the AD1845 in the lowest power consumption mode. XTAL1 is required to be
running during the minimum low pulsewidth of the reset signal.
VREF
32
35
O
Voltage Reference. Nominal 2.25 volt reference available for dc-coupling and level-
shifting. VREF should not be used to sink or source current.
33
38
I
Voltage Reference Filter. Voltage reference filter point for external bypassing only.
VREF_F
Left Channel Filter. This pin requires a 1.0 ?F capacitor to analog ground for proper
L_FILT
31
33
I
operation.
Right Channel Filter. This pin requires a 1.0 ?F capacitor to analog ground for proper
R_FILT
26
25
I
operation.
NC
48?52, 2?5, 21?24
No Connect.
55
26, 27, 32, 34,
36, 37, 39,
50?53, 58?66,
69, 70, 80?83,
94?97
REV. C
?8?
AD1845
Power Supplies
Pin Name
PLCC
TQFP
I/O
Description
35 & 36
41 & 42
I
Analog Supply Voltage (+5 V).
VCC
GNDA
34 & 37
40 & 43
I
Analog Ground.
1, 7, 15,
10, 14,
I
Digital Supply Voltage (+5 V).
VDD
19, 45,
55, 68,
54
88, 98
GNDD
2, 8, 16,
11, 15, 20,
I
Digital Ground.
20, 25,
54, 67,
44, 53,
79, 89,
64
99
(Continued from page 1)
unsigned magnitude PCM linear data, and 8-bit ?-law or A-law
AD1845
AEN
ADDRESS
companded digital data.
18
DECODE
SA19:2
CS
The ∑∆ DACs are preceded by a digital interpolation filter. An
SA1
A1
attenuator provides independent user volume control over each
SA0
A0
IOWC
WR
DAC channel. Nyquist images and shaped quantized noise are
I
IORC
RD
removed from the DACs' analog stereo output by on-chip
S
A
switched-capacitor and continuous-time filters.
8
8
74_245
DATA7:0
DATA7:0
The AD1845 supports multiple low power and power-down
B
DIR
DBDIR
U
modes to support notebook and portable computing multimedia
G
DBEN
S
B
A
applications. The ADC, DAC, and mixer paths can be sus-
DRQ <X>
PDRQ
pended independently allowing the AD1845 to be used for
DRQ <Y>
CDRQ
capture-only or playback-only, lessening power consumption
DAK <X>
PDAK
and extending battery life.
DAK <Y>
CDAK
IRQ <Z>
The AD1845 includes a variable sample frequency generator,
INT
that allows the codec to instantaneously change sample rates
Figure 1. Interface to ISA Bus
with a resolution of 1 Hz without "clicks" and "pops." Addi-
tionally, ∑∆ quantization noise is kept out of the 20 kHz audio
External circuit requirements are limited to a minimal number
band regardless of the chosen sample rate. The codec uses the
of low cost support components. Anti-imaging DAC output
variable sample frequency generator to derive all internal clocks
filters are incorporated on-chip. Dynamic range exceeds 80 dB
from a single external crystal or clock source.
over the 20 kHz audio band. Sample rates from 4 kHz to 50 kHz
are supported from a single external crystal or clock source.
Expanded Mode (MODE2)
MODE1 is the initial state of the AD1845. In this state the
The AD1845 has built-in 8/16 mA (user selectable) bus drivers.
AD1845 appears as an AD1848 compatible device. To access
If 24 mA drive capability is required, the AD1845 generates
the expanded modes of operation on the AD1845, the MODE2
enable and direction controls for IC bus buffers such as the
bit should be set in the Miscellaneous Information Control
74 245.
Register. When this bit is set to one, 16 additional indirect
The codec includes a stereo pair of ∑∆ analog-to-digital con-
registers can be addressed allowing the user to access the
verters and a stereo pair of ∑∆ digital-to-analog converters. The
AD1845's expanded features. The AD1845 can return to
AD1845 mixer surpasses MPC Level-2 recommendations.
MODE1 operation by clearing the MODE2 bit. In both
Inputs to the ADC can be selected from four stereo pairs of
MODE1 and MODE2, the capture and playback FIFOs are
analog signals: line (LINE), microphone (MIC), auxiliary line
active to prevent data loss.
#1 (AUX1), and post-mixed DAC output. A software-con-
The additional MODE2 functions are:
trolled programmable gain stage allows independent gain for
each channel going into the ADC. In addition, the analog mixer
1. Full-Duplex DMA support.
allows the mono input (M_IN), MIC, AUX1, LINE and auxil-
2. MIC input mixer, mute and volume control.
iary line #2 (AUX2) signals to be mixed with the DACs' output.
3. Mono output with mute control.
The ADCs' output can be digitally mixed with the DACs' input.
4. Mono input with mixer volume control.
The pair of 16-bit outputs from the ADCs is available over a
byte-wide bidirectional interface that also supports 16-bit digital
5. Software controlled advanced power-down modes.
input to the DACs and control information. The AD1845 can
6. Programmable sample rates from 4 kHz to 50 kHz in 1 Hz
accept and generate 16-bit twos complement PCM linear digital
increments.
data in both little endian or big endian byte ordering, 8-bit
REV. C
?9?
AD1845
Digital Mixing
FUNCTIONAL DESCRIPTION
Stereo digital output from the ADCs can be digitally mixed with
This section overviews the functionality of the AD1845 and is
the input to the DACs. Digital output from the ADCs going out
intended as a general introduction to the capabilities of the
of the data port is unaffected by the digital mix. Along the
device. As much as possible, detailed reference information has
digital mix datapath, the 16-bit linear output from the ADCs
been placed in "Control Registers" and other sections. The
is attenuated by an amount specified with control bits. Both
user is not expected to refer repeatedly to this section.
channels of the digital mix datapath are attenuated by the same
Analog Inputs
amount. (Note that internally the AD1845 always works with
The AD1845 SoundPort Stereo Codec accepts stereo line-level
16-bit PCM linear data, digital mixing included; format conver-
and microphone-level inputs. The LINE, MIC, AUX1, and
sions take place at the input and output.)
post-mixed DAC output are available to the ADC multiplexer.
Sixty-four steps of ?1.5 dB attenuation are supported to ?94.5 dB.
The DAC output can be mixed with LINE, MIC, AUX1,
The digital mix datapath can also be completely muted. Note
AUX2 and M_IN. Each channel of the MIC inputs can be
that the level of the mixed signal is also a function of the input
amplified by +20 dB to compensate for the difference between
PGA settings, since they affect the ADCs' output.
line levels and typical condenser microphone levels.
The attenuated digital mix data is digitally summed with the
Analog Mixing
DAC input data prior to the DACs' datapath attenuators. The
The M_IN mono input signal, MIC, LINE, AUX1 and AUX2
digital sum of digital mix data and DAC input data is clipped at
analog stereo signals can be mixed in the analog domain with
plus or minus full scale and does not wrap around. Because both
the DAC output. Each channel of each AUX, LINE and MIC
stereo signals are mixed before the output attenuators, mix data is
analog input can be independently gained/attenuated from
attenuated a second time by the DACs' datapath attenuators.
+12 dB to ?34.5 dB in 1.5 dB steps or completely muted.
M_IN can be attenuated from 0 dB to ?45 dB in 3 dB steps or
In case the AD1845 is capturing data, but ADC output data is
muted. The post-mixed DAC outputs are available on L_OUT
not removed in time ("ADC overrun"), the last sample captured
and R_OUT and also to the ADC input multiplexer.
before overrun will be used for the digital mix. In case the
AD1845 is playing back data, but input digital DAC data fails
Even if the AD1845 is not playing back data from its DACs, the
to arrive in time ("DAC underrun"), a midscale zero will be
analog mix function can still be active.
added to the digital mix data when the DACZ control bit is set
Analog-to-Digital Datapath
to 0; otherwise, the DAC will output the previous valid sample
The PGA following the input multiplexer allows independent
in an underrun condition.
selectable gains for each channel from 0 dB to 22.5 dB in
Analog Outputs
+1.5 dB steps. The codec can operate either in a global stereo
Stereo and mono line-level outputs are available at external
mode or in a global mono mode with left-channel inputs
pins. Each channel of this output can be independently muted.
appearing at both channel outputs.
When muted, the outputs will settle to a dc value near VREF, the
The AD1845 ∑∆ ADCs incorporate a fourth-order modulator.
midscale reference voltage. The output is selectable for 2.0 V
A single pole of passive filtering is all that is required for anti-
peak-to-peak or 2.8 V peak-to-peak. When selecting the LINE
aliasing the analog input because of the ADC's high over sam-
output as an input to the ADC, the ADC automatically com-
pling ratio. The ADCs include linear-phase digital decimation
pensates for the output level selection.
filters that low-pass filter the input to 0.4 ?FS. ("FS" is the
Digital Data Types
word rate or "sampling frequency.") ADC input over range
The AD1845 supports five global data types: 16-bit twos comple-
conditions are reported on status bits in the Test and Initializa-
ment linear PCM (little endian and big endian byte ordering),
tion Register.
8-bit unsigned linear PCM, companded ?-law, and 8-bit com-
Digital-to-Analog Datapath
panded A-law, as specified by control register bits. Data in all
The ∑∆ DACs are preceded by a programmable attenuator and
formats is always transferred MSB first. All data formats that are
a low-pass digital interpolation filter. The anti-imaging interpo-
less than 16 bits are MSB-aligned to ensure the use of full
lation filter over samples and digitally filters the higher fre-
system resolution.
quency images. The attenuator allows independent control of
The 16-bit PCM data format is capable of representing 96 dB
each DAC channel from 0 dB to ?94.5 dB in ?1.5 dB steps plus
full mute. The DACs' ∑∆ noise shapers also over sample and
of dynamic range. Eight-bit PCM can represent 48 dB of dy-
namic range. Companded ?-law and A-law data formats use
convert the signal to a single-bit stream. The DAC outputs are
nonlinear coding with less precision for large amplitude signals.
then filtered in the analog domain by a combination of switched-
The loss of precision is compensated for by an increase in dy-
capacitor and continuous-time filters. They remove the very
namic range to 64 dB and 72 dB, respectively.
high frequency components of the DAC bit stream output. No
external components are required.
On input, 8-bit companded data is expanded to an internal
linear representation, according to whether ?-law or A-law was
Changes in DAC output attenuation take effect only on zero
specified in the codec's internal registers. Note that when ?-law
crossings, eliminating "zipper" noise on playback. Each chan-
compressed data is expanded to a linear format, it requires
nel has its own independent zero-crossing detector and attenua-
14 bits. A-law data expanded requires 13 bits.
tor change control circuitry. A timer guarantees that requested
volume changes will occur even in the absence of a zero cross-
ing. The time-out period is 8 milliseconds at a 48 kHz sampling
rate and 48 milliseconds at an 8 kHz sampling rate. (Timeout
[ms] 384 ?font>FS [kHz].)
REV. C
?10?
AD1845
Power Supplies and Voltage Reference
0
15
8 7
COMPRESSED
MSB
LSB
The AD1845 operates from a +5 V power supply. Independent
INPUT DATA
analog and digital supplies are recommended for optimal perfor-
mance though excellent results can be obtained in single-supply
0
15
3/2
2/1
systems. A voltage reference is included on the codec and its
MSB
LSB
EXPANSION
2.25 V buffered output is available on an external pin (VREF).
The reference output can be used for biasing op amps used in
0
15
3/2
2/1
dc coupling. The internal reference is externally bypassed to
MSB
LSB
DAC INPUT
000/00
analog ground at the VREF_F pin.
Figure 2. ?-Law or A-Law Expansion
Clocks and Sample Rates
The AD1845 operates from a single external crystal or clock
When 8-bit companding is specified, the ADCs' linear output is
source. From a single input, a wide range of sample rates can be
compressed to the format specified.
generated. The AD1845 default frequency source is a
24.576 MHz input. The AD1845 can also be driven from a
0
15
14.31818 MHz (OSC), 24 MHz, 25 MHz or 33 MHz input
MSB
LSB
ADC OUTPUT
frequency source. In MODE1, the input drives the internal
variable sample frequency generator to derive the following
15
0
3/2
2/1
AD1848 compatible sample rates: 5.5125, 6.615, 8, 9.6,
MSB
LSB
TRUNCATION
11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1,
48 kHz. In MODE2, the AD1845 can be programmed to gen-
erate any sample frequency between 4 kHz and 50 kHz with
0
15
8 7
1 Hz resolution. Note that it is no longer required to enter
MSB
LSB
COMPRESSION
00000000
Mode Change Enable (MCE) to change the sample rate. This
Figure 3. ?-Law or A-Law Compression
feature allows the user to change the AD1845's sample rate "on
the fly."
Note that all format conversions take place at input or output.
Internally, the AD1845 always uses 16-bit linear PCM represen-
tations to maintain maximum precision.
CONTROL REGISTERS
Control Register Architecture
Timer Registers
The AD1845 SoundPort Stereo Codec accepts both data and
The timer registers are provided for system level synchroniza-
control information through its byte-wide parallel port. Indirect
tion, and for periodic interrupt generation. The 16-bit timer
addressing minimizes the number of external pins required to
time base is determined by the frequency of the connected input
access all 37 of its byte-wide internal registers. Only two exter-
clock source.
nal address pins, ADR1:0, are required to accomplish all data
The timer is enabled by setting the Timer Enable bit, TE, in the
and control transfers. These pins select one of five direct regis-
Alternate Feature Enable register. To set the timer, load the
ters. (ADR1:0 = 3 addresses two registers, depending on
Upper and Lower Timer Bits Registers. The timer value will
whether the transfer is for a playback or capture.)
then be loaded into an internal count register with a value of
approximately 10 ?s (the exact timer value is listed in the regis-
ADR1:0
Register Name
ter descriptions). The internal count register will decrement
0
Index Address Register
until it reaches zero, then the Timer Interrupt bit, TI, is set and
1
Indexed Data Register
an interrupt will be sent to the host. The next timer clock will
2
Status Register
load the internal count register with the value of the Timer
3
PIO Data Register
Register, and the timer will be reinitialized. To clear the inter-
rupt, write to the Status Register or write a "0" to TI.
Figure 4. Direct Register Map
Interrupts
The AD1845 supports interrupt conditions generated by DMA
playback count expiration, DMA capture count expiration, or
timer expiration. The INT bit will remain set, HI, until a write
has been completed to the Status Register or by clearing the TI,
CI, or PI bit (depending on the existing condition) in the Cap-
ture Playback Timer Register. The IEN bit of the Pin Control
Register determines whether the interrupt pin responds to an
interrupt condition and reflects the interrupt state on the
INT status bit.
REV. C
?11?
AD1845
A write to or a read from the Indexed Data Register will access the Indirect Register which is indexed by the value most recently
written to the Index Address Register. The Status Register and the PIO Data Register are always accessible directly, without
indexing. The 32 Indirect Register indexes are shown in Figure 5:
Index
Register Name
Reset/Default State
0
Left Input Control
000x
0000
1
Right Input Control
000x
0000
2
Left Aux #1 Input Control
1xx0
1000
3
Right Aux #1 Input Control
1xx0
1000
4
Left Aux #2 Input Control
1xx0
1000
5
Right Aux #2 Input Control
1xx0
1000
6
Left Output Control
1x00
0000