Ij

SigmaDSPTM Multichannel
28-Bit Audio Processor
AD1940
FEATURES
APPLICATIONS
16-channel digital audio processor
Automotive sound systems
Accepts sample rates up to 192 kHz
Digital televisions
28-bit ?28-bit multiplier with full 56-bit accumulator
Home theater systems (Dolby Digital/DTS postprocessor)
Fully-programmable program RAM for custom
Multichannel audio systems
program download
Mini-component stereos
Parameter RAM allows complete control of 1,024 parameters
Multimedia audio
Control port features safeload for transparent parameter
Digital speaker crossover
updates and complete mode and memory transfer control
Musical instruments
Target/slew RAM for click-free volume control and dynamic
In-seat sound systems (aircrafts/motor coaches)
parameter updates
Double precision mode for full 56-bit processing
FUNCTIONAL BLOCK DIAGRAM
PLL for generating MCLK from 64 ?fS, 256 ?fS, 384 ?fS, or
512 ?fS clocks
4
Hardware-accelerated DSP core
AD1940
21 kB (6,144 words) data memory for up to 128 ms of audio
VOLTAGE
delay at fs = 48 kHz
REGULATOR
Flexible serial data port with I2S compatible, left-justified,
28 ?28
2
and right-justified serial port modes
DSP CORE
2
SERIAL DATA/
8- and 16-channel TDM input/output modes
TDM INPUTS
2
On-chip voltage regulator for compatibility with 3.3 V and
DATA FORMAT:
SERIAL
5 V systems
DATA/
5.23 (SINGLE
TDM
MASTER
Programmable low power mode
PRECISION)
PLL
OUTPUTS
CLOCK
Fast start-up and boot time from power on or reset
INPUT
10.46 (DOUBLE
PRECISION)
48-lead LQFP plastic package
SERIAL
4
CONTROL
SPI I/O
RAM
ROM
INTERFACE
Figure 1.
GENERAL DESCRIPTION
The AD1940 is a complete 28-bit, single-chip, multichannel
The AD1940 is a fully-programmable DSP. Easy to use software
audio DSP for equalization, multiband dynamics processing,
allows the user to graphically configure a custom signal
delay compensation, speaker compensation, and image
processing flow using blocks such as biquad filters, dynamics
enhancement. These algorithms can be used to compensate for
processors, and surround sound processors. An extensive
the real-world limitations of speakers, amplifiers, and listening
control port allows click-free parameter updates, along with
readback capability from any point in the algorithm flow.
environments, resulting in a dramatic improvement of
perceived audio quality.
The AD1940's digital input and output ports allow a glueless
The signal processing used in the AD1940 is comparable to that
connection to ADCs and DACs by multiple, 2-channel serial
found in high end studio equipment. Most of the processing is
data streams or TDM data streams. When in TDM mode, the
done in full, 56-bit double-precision mode, resulting in very
AD1940 can input 8 or 16 channels of serial data, and can
good low level signal performance and the absence of limit
output either 8 or 16 channels of serial data. The input and
cycles or idle tones. The dynamics processor uses a sophisti-
output port configurations can be individually set. The AD1940
is controlled via a 4-wire SPI port.
cated, multiple-breakpoint algorithm often found in high end
broadcast compressors.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Specifications subject to change without notice. No license is granted by implication
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Fax: 781.326.8703
? 2004 Analog Devices, Inc. All rights reserved.
registered trademarks are the property of their respective owners.
AD1940
TABLE OF CONTENTS
Specifications..................................................................................... 3
RAMs and Registers ....................................................................... 16
Digital I/O ..................................................................................... 3
Control Port Addressing............................................................ 16
Power.............................................................................................. 3
Parameter RAM Contents......................................................... 16
Temperature Range ...................................................................... 3
Recommended Program/Parameter Loading Procedures.... 17
Digital Timing............................................................................... 4
Target/Slew RAM ....................................................................... 17
PLL ................................................................................................. 4
Safeload Registers ....................................................................... 19
Regulator........................................................................................ 4
Data Capture Registers .............................................................. 20
Absolute Maximum Ratings............................................................ 5
DSP Core Control Register ....................................................... 20
ESD Caution.................................................................................. 5
RAM Configuration Register ................................................... 21
Digital Timing Diagrams................................................................. 6
Control Port Read/Write Data Formats .................................. 22
Pin Configuration and Function Descriptions............................. 8
Serial Data Input/Output Ports .................................................... 24
Features ............................................................................................ 10
Serial Output Control Registers ............................................... 26
Pin Functions .............................................................................. 11
Serial Input Control Register .................................................... 26
Signal Processing ............................................................................ 13
Initialization .................................................................................... 29
Overview...................................................................................... 13
Power-Up Sequence ................................................................... 29
Numeric Formats........................................................................ 13
Setting Master Clock/PLL Mode.............................................. 29
Programming .............................................................................. 13
Voltage Regulator ....................................................................... 29
Control Port..................................................................................... 14
Outline Dimensions ....................................................................... 30
Overview...................................................................................... 14
Ordering Guide .......................................................................... 30
REVISION HISTORY
7/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD1940
SPECIFICATIONS
Test conditions, unless otherwise noted.
Table 1.
Parameter
Conditions
Supply Voltage (VDD)
2.5 V
PLL Voltage (PLL_VDD)
2.5 V
Output Voltage (ODVDD)
5.0 V
INVDD Voltage
5.0 V
Ambient Temperature
25?C
Master Clock Input
3.072 MHz, 64 ?fs mode
Load Capacitance
50 pF
Load Current
?1 mA
Input Voltage, HI
2.4 V
Input Voltage, LO
0.8 V
DIGITAL I/O
Table 2. Digital I/O1
Parameter
Min
Max
Unit
Input Voltage, HI (VIH)
2.1
V
Input Voltage, LO (VIL)
0.8
V
Input Leakage (IIH)
10
?A
Input Leakage (IIL)
10
?A
High Level Output Voltage (VOH) ODVDD = 4.5 V, IOH = 1 mA
3.9
V
High Level Output Voltage (VOH) ODVDD = 3.0 V, IOH = 1 mA
2.6
V
Low Level Output Voltage (VOL) ODVDD = 4.5 V, IOL = 1 mA
0.4
V
Low Level Output Voltage (VOL) ODVDD = 3.0 V, IOL = 1 mA
0.3
V
Input Capacitance
5
pF
All measurements across -40?C to 125?C (case) and across VDD = 2.25 V to 2.75 V.
1
POWER
Table 3.
Max1
Parameter
Min
Typ
Unit
Supplies
Voltage
2.25
2.5
2.75
V
1552
Digital Current
92
mA
PLL Current
3.5
8
mA
4.53
133
Digital Current, Reset
mA
PLL Current, Reset
3
8.5
mA
Dissipation
Operation, all supplies
238.8
mW
Reset, all supplies
10.8
mW
Maximum specifications are measured across -40?C to 125?C (case) and across VDD = 2.25 V to 2.75 V.
1
2
Measurement running a typical large program that writes to all 16 outputs with 0 dB digital sine waves applied to all eight inputs. Your program may differ.
3
The digital reset current is specified for the given test conditions. This current scales with the input MCLK rate, so higher input clocks draw more current while in reset.
TEMPERATURE RANGE
Table 4.
Parameter
Min
Typ
Max
Unit
Functionality Guaranteed
?40
+105
?C Ambient
?40
+125
?C Case
Rev. 0 | Page 3 of 32
AD1940
DIGITAL TIMING
Table 5 Digital Timing1
Parameter
Comments
Min
Max
Unit
tMP
MCLK Period
512 fS mode
36
244
ns
tMP
MCLK Period
384 fS mode
48
366
ns
tMP
MCLK Period
256 fS mode
73
488
ns
tMP
MCLK Period
64 fS mode
291
1953
ns
tMP
MCLK Period
Bypass mode
12
ns
tMDC
MCLK Duty Cycle
Bypass mode
40
60
%
tBIL
BCLK_IN LO Pulse Width
4
ns
tBIH
BCLK_IN HI Pulse Width
2
ns
tLIS
LRCLK_IN Setup
To BCLK_IN rising
12
ns
tLIH
LRCLK_IN Hold
From BCLK_IN rising
0
ns
tSIS
SDATA_INx Setup
To BCLK_IN rising
3
ns
tSIH
SDATA_INx Hold
From BCLK_IN rising
2
ns
tLOS
LRCLK_OUTx Setup
Slave mode
2
ns
tLOH
LRCLK_OUTx Hold
Slave mode
2
ns
BCLK_OUTx Falling to
tTS
2
ns
LRCLK_OUTx Timing Skew
tSODS
SDATA_OUTx Delay
Slave mode, from BCLK_OUTx falling
17
ns
tSODM
SDATA_OUTx Delay
Master mode, from BCLK_OUTx falling
17
ns
1 ?INTMCLK (14)2
tCCPL
CCLK Pulse Width LO
ns
1 ?INTMCLK (14)2
tCCPH
CCLK Pulse Width HI
ns
tCLS
CLATCH Setup
To CCLK rising
0
ns
2 ?INTMCLK + 4 (32)2
tCLH
CLATCH Hold
From CCLK rising
ns
2 ?INTMCLK (28)2
tCLPH
CLATCH Pulse Width HI
ns
tCDS
CDATA Setup
To CCLK rising
0
ns
2 ?INTMCLK + 2 (30)2
tCDH
CDATA Hold
From CCLK rising
ns
4 ?INTMCLK +18 (74)2
tCOD
COUT Delay
From CCLK rising
ns
tRLPW
RESETB LO Pulse Width
10
ns
1
All timing specifications are given for the default (I2S) states of the serial input control port and the serial output control ports. See Table 32.
2
These specifications are based on the internal master clock period in a specific application. In normal operation, the master clock runs at 1,536 ?fs, so the internal master
clock at fs = 48 kHz has a 14 ns period. The values in parentheses are the timing values for fs = 48 kHz.
PLL
Table 6.
Parameter
Min
Typ
Max
Unit
Lock Time
3
20
ms
REGULATOR
Table 7.
Parameter
Min
Typ
Max
Unit
VSENSE Output Voltage
2.25
2.5
2.68
V
Rev. 0 | Page 4 of 32
AD1940
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter
Min
Max
Unit
VDD to DGND
?0.3
+3.0
V
PLL_ VDD to PGND
?0.3
+3.0
V
OD VDD to DGND
?0.3
+6.0
V
INVDD to DGND
ODVDD
+6.0
V
Digital Inputs
DGND ? 0.3
INVDD + 0.3
V
Maximum Junction Temperature
135
?C
Storage Temperature Range
?65
+150
?C
Soldering (10 sec)
300
?C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 9. Package Characteristics
Parameter
Min
Typ
Max
Unit
θJA Thermal Resistance (Junction-to-Ambient)
72
?C/W
θJC Thermal Resistance (Junction-to-Case)
19.5
?C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 32
AD1940
DIGITAL TIMING DIAGRAMS
tLIH
tBIH
BCLK_IN
tBIL
tLIS
LRCLK_IN
tSIS
SDATA_INX
LEFT-JUSTIFIED
MSB
MSB-1
MODE
tSIH
tSIS
SDATA_INX
I2S-JUSTIFIED
MSB
MODE
tSIH
tSIS
tSIS
SDATA_INX
RIGHT-JUSTIFIED
LSB
MSB
MODE
tSIH
tSIH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Serial Input Port Timing
tLCH
tBIH
tTS
BCLK_OUTX
tBIL
tLOS
LRCLK_OUTX
tSDDS
tSDDM
SDATA_OUTX
LEFT-JUSTIFIED
MSB
MSB-1
MODE
tSDDS
tSDDM
SDATA_OUTX
I2S-JUSTIFIED
MSB
MODE
tSDDS
tSDDM
SDATA_OUTX
RIGHT-JUSTIFIED
LSB
MSB
MODE
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 3. Serial Output Port Timing
Rev. 0 | Page 6 of 32
AD1940
tCLS
tCLH
tCLPH
tCCPL
tCCPH
CLATCH
CCLK
CDATA
tCDH
tCDS
COUT
tCOD
Figure 4. SPI Port Timing
tMP
MCLK
RESETB
tRLPW
Figure 5. Master Clock and Reset Timing
Rev. 0 | Page 7 of 32
AD1940
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
VDD 1
36 GND
PIN 1
MCLK 2
INDICATOR
35 BCLK_OUT1
RESERVED 3
34 LRCLK_OUT1
PLL_CTRL0 4
33 ODVDD
PLL_CTRL1 5
32 SDATA_OUT3
AD1940
PLL_CTRL2 6
31 SDATA_OUT2
TOP VIEW
PLL_GND 7
30 SDATA_OUT1
(Not to Scale)
PLL_VDD 8
29 SDATA_OUT0
NC
9
28 ODVDD
LRCLK_IN 10
27 BCLK_OUT0
BCLK_IN 11
26 LRCLK_OUT0
GND 12
25 VDD
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
Figure 6. 48-Lead LQFP Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
I/O
Mnemonic
Description
1, 25, 37
VDD
Core Power.
2
IN
MCLK
Master Clock Input.
3
RESERVED
This pin should be connected to ground.
4
IN
PLL_CTRL0
PLL Control 0.
5
IN
PLL_CTRL1
PLL Control 1.
6
IN
PLL_CTRL2
PLL Control 2.
7
PLL_GND
PLL Ground.
8
PLL_VDD
PLL Power.
9
NC
No Connect.
10
IN
LRCLK_IN
Left/Right Clock for Serial or TDM Data Inputs.
11
IN
BCLK_IN
Bit Clock for Serial or TDM Data Inputs.
12, 24, 36, 48
GND
Digital Ground.
13
VDD
Core Power.
14
IN
SDATA_IN0
Serial Data Input 0.
15
IN
SDATA_IN1
Serial Data Input 1.
16
IN
SDATA_IN2/TDM_IN1
Serial Data Input 2/TDM Input 1.
17
IN
SDATA_IN3/TDM_IN0
Serial Data Input 3/TDM Input 0.
18
IN
ADR_SEL
Control Port Address Select.
19
OUT
COUT
SPI Data Output.
20
IN
CCLK
SPI Clock.
21
IN
CLATCH
SPI Data Latch.
22
IN
CDATA
SPI Data Input.
23
IN
RESETB
Reset the AD1940
26
IN/OUT
LRCLK_OUT0
Left/Right Clock Output 0.
27
IN/OUT
BCLK_OUT0
Bit Clock Output 0.
28, 33, 40
ODVDD
Power Connection for Output Pins.
29
OUT
SDATA_OUT0/TDM_O0
Serial Data Output 0/TDM (16- or 8-Channel) Output 0.
30
OUT
SDATA_OUT1
Serial Data Output 1.
Rev. 0 | Page 8 of 32
AD1940
Pin No.
I/O
Mnemonic
Description
31
OUT
SDATA_OUT2
Serial Data Output 2.
32
OUT
SDATA_OUT3
Serial Data Output 3.
34
IN/OUT
LRCLK_OUT1
Left/Right Clock Output 1.
35
IN/OUT
BCLK_OUT1
Bit Clock Output 1.
38
OUT
SDATA_OUT4/TDM_O1
Serial Data Output 4/TDM (8-Channel) Output 1.
39
OUT
SDATA_OUT5
Serial Data Output 5.
41
OUT
SDATA_OUT6
Serial Data Output 6.
42
OUT
SDATA_OUT7/DCSOUT
Serial Data Output 7/Data Capture Output.
43
INVDD
Input Voltage Reference.
44
IN
VSUPPLY
Voltage Level Input to Regulator. Usually 3.3 V or 5 V.
45
IN
VSENSE
Digital Power Level. Should be tied to VDD.
46
OUT
VDRIVE
Drive for External PNP Transistor.
47
OUT
VREF
Reference Level for Voltage Regulator.
Rev. 0 | Page 9 of 32
AD1940
FEATURES
The core of the AD1940 is a 28-bit DSP (56-bit with double
The AD1940 contains eight independent data capture circuits
precision) optimized for audio processing.
that can be programmed to tap the signal flow of the processor
at any point in the DSP algorithm flow. Six of these captured
The AD1940 contains a program RAM that is initialized from
signals can be accessed by reading from the data capture
an internal program ROM on power-up. The program RAM
registers through the control port. The remaining two data
can be loaded with a custom program after power-up. Signal
capture registers can be used to send any internal captured
processing parameters are stored in a 1024-location parameter
signal to a stereo digital output signal on Pin SDATA_OUT7 for
RAM, which is initialized on power-up by an internal boot-
driving external DACs or digital analyzers.
ROM. New values are written to the parameter RAM using the
control port. The values stored in the parameter RAM control
The AD1940 has very flexible serial data input/output ports that
individual signal processing blocks, such as IIR equalization
allows for glueless interconnection to a variety of ADCs, DACs,
filters, dynamics processors, audio delays, and mixer levels. A
general-purpose DSPs, S/PDIF receivers, and sample rate
converters. The AD1940 can be configured in I2S, left-justified,
safeload feature allows parameters to be transparently updated
without causing clicks on the output signals.
right-justified, or TDM serial port compatible modes. It can
support 16, 20, and 24 bits in all modes. The AD1940 accepts
The target/slew RAM contains 64 locations and can be used as
serial audio data in MSB first and twos complement format.
channel volume controls or for other parameter updates. These
The AD1940 operates from a single 2.5 V power supply. It is
RAM locations take a target value for a given parameter and
fabricated on a single monolithic integrated circuit and is
ramp the current parameter value to the new value using a
housed in a 48-lead LQFP package for operation over the
specified time constant and one of a selection of linear or
?40?C to +105?C temperature range.
logarithmic curves.
The AD1940 has a sophisticated control port that supports
complete read/write capability of all memory locations. Five
control registers (core, RAM configuration, Serial Output 0 to 7,
Serial Output 8 to 15, and serial input) are provided to offer
complete control of the chip's configuration and serial
modes. Handshaking is included for ease of memory
uploads/downloads.
2
DATA MEMORY
2
6k ?28
28 ?28
TARGET/SLEW
RAM
DSP CORE
64 ?28
2
SERIAL
SERIAL DATA/
DATA/TDM
TDM OUTPUT
DATA FORMAT:
INPUT
GROUP
5.23 (SINGLE PRECISION)
GROUP
10.46 (DOUBLE PRECISION)
2
PLL MODE
MCLK
SELECT
PLL
MASTER
CLOCK
CONTROL
INPUT
REGISITER
COEFFICIENT
PARAMETER
PROGRAM
ROM
RAM
RAM
SERIAL
4
TRAP REG.
SPI I/O
512 ?28
1024 ?28
1536 ?40
CONTROL
GROUP
PORT
SAFELOAD
REGISTER
RESETB
4
REGULATOR
MEMORY CONTROLLERS
VOLTAGE REGULATOR
GROUP
Figure 7. Block Diagram
Rev. 0 | Page 10 of 32
AD1940
PIN FUNCTIONS
LRCLK_OUT0
Table 10 shows the AD1940's pin numbers, names, and
BCLK_OUT0
functions. Input pins have a logic threshold compatible with
Output Clocks. This clock pair is used for outputs
TTL input levels and may be used in systems with 3.3 V or
SDATA_OUT0?3. In slave mode, these clocks are inputs
5 V logic.
to the AD1940. On power-up, these pins are set to slave
SDATA_IN0
mode to avoid conflicts with external master-mode devices.
SDATA_IN1
SDATA_IN2/TDM_IN1
LRCLK_OUT1
SDATA_IN3/TDM_IN0
BCLK_OUT1
Serial Data/TDM Inputs. The serial format is selected by writing
Output Clocks. This clock pair is used for outputs
to Bits 2:0 of the serial input port control register. SDATA_IN2
SDATA_OUT4?7. In slave mode, these clocks are inputs
and SDATA_IN3 are dual-function pins that can be set to a
to the AD1940. On power-up, these pins are set to slave
mode to avoid conflicts with external master-mode devices.
variety of standard 2-channel formats or to TDM mode. Two of
these four pins (SDATA_IN2 and SDATA_IN3) can be used as
MCLK
TDM inputs in either dual-wire 8-channel mode or single-wire
Master Clock Input. The AD1940 uses a PLL to generate the
16-channel mode (TDM_O0 only). In dual-wire 8-channel
appropriate internal clock for the DSP core. An in-depth
mode, Channels 0-7 will be input on SDATA_IN3 and
description of using the PLL is found in the Setting Master
Channels 8-15 on SDATA_IN2. In single-wire 16-channel
Clock/PLL Mode section.
mode, Channels 0-15 will be input on SDATA_IN2. See the
PLL_CTRL0
Serial Data Input/Output Ports section for further explanation.
PLL_CTRL1
LRCLK_IN
PLL_CTRL2
BCLK_IN
PLL Mode Control Pins. The functionality of these pins is
Left/Right and Bit Clocks for Timing the Input Data. These
described in the Setting Master Clock/PLL Mode section.
input clocks are associated with the SDATA_IN0-3 signals. The
CDATA
input port is always in a slave configuration. These pins also
Serial Data Input for the SPI Control Port.
function as frame sync and bit clock for the input TDM stream.
COUT
SDATA_OUT0/TDM_O0
SDATA_OUT1
Serial Data Output for the SPI Port. This is used for reading
SDATA_OUT2,
back registers and memory locations. It is three-stated when an
SDATA_OUT3
SPI read is not active.
SDATA_OUT4/TDM_O1
SDATA_OUT5
CCLK
SDATA_OUT6
SPI Bit Clock. This clock may either run continuously or be
SDATA_OUT7/DCSOUT
gated off in between SPI transactions.
Serial Data/TDM/Data Capture Outputs. These pins are used
CLATCH
for serial digital outputs. For non-TDM systems, these eight
SPI Latch Signal. This must go low at the beginning of an SPI
pins can output 16 channels of digital audio, using a variety of
transaction and high at the end of a transaction. Each SPI
standard two-channel formats. They are grouped into two
transaction may take a different number of CCLKs to complete,
groups of four pins (0-3 and 4-7); each group can be indepen-
depending on the address and read/write bit that are sent at the
dently set to any of the available serial modes, allowing the
beginning of the SPI transaction.
AD1940 to simultaneously communicate with two external
devices with different serial formats. Two of these eight pins
ADR_SEL
(SDATA_OUT0 and SDATA_OUT4) can be used as TDM
Address Select. This pin selects the address for the AD1940's
outputs in either dual-wire 8-channel mode or single-wire
communication with the control port. This allows two AD1940s
16-channel mode (TDM_OUT0 only). In dual-wire 8-channel
to be used with a single CLATCH signal.
mode, Channels 0-7 will be output on SDATA_OUT0 and
Channels 8-15 on SDATA_OUT4. See the Serial Data
Input/Output Ports section for further explanation.
SDATA_OUT7 can also be used as a data capture output, as
described in the Data Capture Registers section.
Rev. 0 | Page 11 of 32
AD1940
VDD (4)
RESETB
Digital VDD for Core. 2.5 V nominal.
Active-Low Reset Signal. After RESETB goes high, the AD1940
goes through an initialization sequence where the program and
GND (4)
parameter RAMs are initialized with the contents of the on-
Digital Ground.
board boot ROMs. All registers are set to 0, and the data
PLL_VDD
RAMs are also set to 0. The initialization is complete after
8,192 internal MCLK cycles (referenced to the rising edge of
Supply for AD1940 PLL. 2.5 V nominal.
RESETB), which corresponds to 1,366 external MCLK cycles if
PLL_GND
the part is in 256 ?fS mode. New values should not be written to
PLL Ground.
the control port until the initialization is complete.
ODVDD (3)
VREF
VDD for All Digital Outputs. The high levels of the digital
Voltage Reference for Regulator. This pin is driven by an
output signals are set on this pin. The voltage can range from
internal 1.15 V reference voltage.
2.5 V to 5.0 V.
VDRIVE
INVDD
Drive for External Transistor. The base of the voltage regulator's
Peak Input Voltage Level. The highest voltage level that the
external PNP transistor is driven from this pin.
input pins will see should be connected to INVDD. This is to
VSENSE
protect the chip inputs from voltage overstress. The voltage on
Digital power level. The voltage level on the VDD pins is sensed
this pin must always be at or above the level of ODVDD.
on VSENSE. VSENSE should be tied to VDD.
VSUPPLY
Main Supply Voltage Level. This pin is tied to the board's main
voltage supply. This is usually 3.3 V or 5 V.
Rev. 0 | Page 12 of 32
AD1940
SIGNAL PROCESSING
4-BIT SIGN EXTENSION
OVERVIEW
DIGITAL
SIGNAL PROCESSING
The AD1940 is designed to provide all signal processing
DATA IN
SERIAL PORT
CLIPPER
(5.23 FORMAT)
functions commonly used in stereo or multichannel playback
5.23
1.23
1.23
5.23
Figure 8. Numeric Precision and Clipping Structure
systems. The signal processing flow is set by using the ADI-
PROGRAMMING
supplied software, which allows graphical entry and real-time
control of all signal processing functions.
On power-up, the AD1940's default program passes the unpro-
cessed input signals to the outputs but the outputs come up
Many of the signal processing functions are coded using full,
muted by default (see Power-Up Sequence section). There are
56-bit double-precision arithmetic. The input and output word
1,536 instruction cycles per audio sample, resulting in an inter-
lengths are 24 bits. Four extra headroom bits are used in the
nal clock rate of 73.728 MHz (for fs = 48 kHz). This DSP runs in
processor to allow internal gains up to 24 dB without clipping.
a stream-oriented manner, meaning all 1,536 instructions are
Additional gains can be achieved by initially scaling down the
executed each sample period. The AD1940 may also be set
input signal in the signal flow.
up to accept double or quad-speed inputs by reducing the
number of instructions/sample, which can be set in the core
The signal processing blocks can be arranged in a custom pro-
control register.
gram that can be loaded to the AD1940's RAM. The available
signal processing blocks are explained in the following sections.
The part can be programmed easily using graphical tools pro-
NUMERIC FORMATS
vided by Analog Devices. No knowledge of writing DSP code is
needed to program this part. The user can simply connect
It is common in DSP systems to use a standardized method of
graphical blocks such as biquad filters, dynamics processors,
specifying numeric formats. Fractional number systems are
mixers, and delays in a signal flow schematic, compile the
specified by an A.B format, where A is the number of bits to the
design, and load the program and parameter files into the
left of the decimal point and B is the number of bits to the right
AD1940's Program RAM through the control port. Signal
of the decimal point.
processing blocks available in the provided libraries include
The AD1940 uses the same numeric format for both the coeffi-
?
Single- and double-precision biquad filters
cient values (stored in the parameter RAM) and the signal data
values. The format is as follows:
?
Mono and multichannel dynamics processors
Numerical Format: 5.23
?
Mixers and splitters
Range: ?16.0 to (+16.0 - 1 LSB)
?
Tone and noise generators
Examples:
1000000000000000000000000000 = ?16.0
?
First-order filters
1110000000000000000000000000 = ?4.0
?
1111100000000000000000000000 = ?1.0
Fixed and variable gain
1111111000000000000000000000 = ?0.25
?
RMS look-up tables
1111111111111111111111111111 = (1 LSB below 0.0)
0000000000000000000000000000 = 0.0
?
Loudness
0000001000000000000000000000 = 0.25
0000100000000000000000000000 = 1.0
?
Delay
0010000000000000000000000000 = 4.0
?
0111111111111111111111111111 = (16.0 ? 1 LSB).
Stereo enhancement (Phat StereoTM)
?
The serial port accepts up to 24 bits on the input and is sign-
Interpolators and Decimators
extended to the full 28 bits of the core. This allows internal
More blocks are always in development. Analog Devices also
gains of up to 24 dB without encountering internal clipping.
provides proprietary and third-party algorithms for applications
A digital clipper circuit is used between the output of the DSP
such as matrix decoding, bass enhancement, and surround
core and the serial output ports (see Figure 8). This clips the top
virtualizers. Please contact ADI for information about licensing
four bits of the signal to produce a 24-bit output with a range of
these algorithms.
1.0 (minus 1 LSB) to ?1.0.
Rev. 0 | Page 13 of 32
AD1940
CONTROL PORT
device, such as a microcontroller, on CCLK's rising edge. The
OVERVIEW
CDATA signal carries the serial input data, and the COUT
The AD1940 has many different control options that can be set
signal is the serial output data. The COUT signal remains three-
through an SPI interface. Most signal processing parameters are
stated until a read operation is requested. This allows other SPI-
controlled by writing new values to the parameter RAM using
compatible peripherals to share the same readback line. All SPI
the control port. Other functions, such as mute and input/
transactions follow the same basic format, shown in Table 11. A
output mode control, are programmed by writing to the
timing diagram is shown in Figure 4. All data written should be
control registers.
MSB-first.
The control port is capable of full read/write operation for all of
Table 11. Generic SPI Word Format
the memories and registers. All addresses may be accessed in
Byte 4,
Byte 0
Byte 1
Byte 2
Byte 3
etc.
both a single-address mode or a burst mode. A control word
consists of the chip address, the register/RAM subaddress, and
chip_adr [6:0],
0000,
adr[7:0]
data
data
R/W
adr[11:8]
the data to be written. The data can be variable in its byte width.
The first byte of a control word (Byte 0) contains the 7-bit chip
Chip Address R/W
address plus the R/W bit. The next two bytes (Bytes 1 and 2)
The first byte of an SPI transaction includes the 7-bit chip
together form the subaddress of the memory or register
address and a R/W bit. The chip address is set by the ADR_SEL
location within the AD1940. This subaddress needs to be two
pin. This allows two AD1940s to share a CLATCH signal, yet
bytes because the memories within the AD1940 are directly
still operate independently. When ADR_SEL is low, the chip
addressable, and their sizes exceed the range of single-byte
address is 0000000; when it is high, the address is 0000001. The
addressing. All subsequent bytes (Bytes 3, 4, etc.) contain the
LSB of this first byte determines whether the SPI transaction is
data, such as control port data or program or parameter data.
a read (Logic Level 1) or a write (Logic Level 0).
The AD1940 has several mechanisms for updating signal
RAM/Register Address
processing parameters in real time without causing pops or
The 12-bit RAM/register address word is decoded into a
clicks. In cases where large blocks of data need to be down-
location in one of the memories or registers.
loaded, the output of the DSP core can be halted (using Bit 9 of
Data Bytes
the core control register), new data loaded, and then restarted.
The number of data bytes varies according to the register or
This is typically done during the booting sequence at start-up or
memory being accessed. In burst write mode, an initial address
when loading a new program into RAM. In cases where only a
is given followed by a continuous sequence of data for
few parameters need to be changed, they can be loaded without
consecutive memory/register locations. The detailed data
halting the program. To avoid unwanted side effects while
format diagram for continuous-mode operation is given in the
loading parameters on the fly, the SigmaDSP provides the
Control Port Read/Write Data Formats section.
safeload registers. The safeload registers can be used to buffer a
full set of parameters (e.g. the five coefficients of a biquad) and
A sample timing diagram for a single SPI write operation to the
then transfer these parameters into the active program within
parameter RAM is shown in Figure 9. A sample timing diagram
one audio frame. The safeload mode uses internal logic to
of a single SPI read operation is shown in Figure 10. The COUT
prevent contention between the DSP core and the control port.
pin goes from three-state to driven at the beginning of Byte 3.
In this example, Bytes 0 to 2 contain the addresses and R/W bit,
The SPI port uses a 4-wire interface, consisting of CLATCH,
and subsequent bytes carry the data. The exact formats for
CCLK, CDATA, and COUT signals. The CLATCH signal goes
specific types of writes are shown in Table 21 to Table 30.
low at the beginning of a transaction and high at the end of a
transaction. The CCLK signal latches CDATA on a low-to-high
transition. COUT data is shifted out of the AD1940 on the
falling edge of CCLK and should be clocked into the receiving
Rev. 0 | Page 14 of 32
AD1940
CLATCH
CCLK
BYTE 0
BYTE 1
BYTE 2
BYTE 3
CDATA
Figure 9. Sample of SPI WRITE format (Single-Write Mode)
CLATCH
CCLK
BYTE 1
BYTE 0
CDATA
HI-Z
HI-Z
COUT
DATA
DATA
DATA
Figure 10. Sample of SPI READ Format (Single-Read Mode)
Rev. 0 | Page 15 of 32
AD1940
RAMS AND REGISTERS
Table 12. Control Port Addresses
SPI Address
Register Name
Read/Write Word Length
0?1023 (0x0000?0x03FF)
Parameter RAM
Write: 4 Bytes, Read: 4 Bytes
1024?2559 (0x0400?0x09FF)
Program RAM
Write: 5 Bytes, Read: 5 Bytes
2560?2623 (0x0A00?0x0A3F)
Target/Slew RAM
Write: 5 Bytes, Read: N/A
2624?2628 (0x0A40?0x0A44)
Parameter RAM Data Safeload Registers 0?4
Write: 5 Bytes, Read: N/A
2629?2633 (0x0A45?0x0A49)
Parameter RAM Indirect Address Safeload Registers 0-4
Write: 2 Bytes, Read: N/A
2634?2639 (0x0A4A?0x0A4F)
Data Capture Registers 0?5 (Control Port Readback)
Write: 2 Bytes, Read: 3 Bytes
2640?2641 (0x0A50?0x0A51)
Data Capture Registers (Digital Output)
Write: 2 Bytes, Read: N/A
2642 (0x0A52)
DSP Core Control Register
Write: 2 Bytes, Read: 2 Bytes
2643 (0x0A53)
RAM Configuration Register
Write: 1 Byte, Read: 1 Byte
2644 (0x0A54)
Serial Output Control Register 1 (Channels 0?7)
Write: 2 Bytes, Read: 2 Bytes
2645 (0x0A55)
Serial Output Control Register 2 (Channels 8?15)
Write: 2 Bytes, Read: 2 Bytes
2646 (0x0A56)
Serial Input Control Register
Write: 1 Byte, Read: 1 Byte
Table 13. RAM Read/Write Modes
SPI Address
Burst Mode
Memory
Size
Read
Write
Write Modes
Range
Available?
Direct Write1 Safeload Write
Parameter RAM
1024 ?28
Yes
Yes
Yes
0?1023
(0x0000?0x03FF)
Direct Write1
Program RAM
1536 ?40
Yes
Yes
Yes
1024?2559
(0x0400?0x09FF)
Yes2
Target/Slew RAM
64 ?34
No
Safeload Write
2560?2623
Yes (via
(0x0A00?0x0A3F)
Safeload)
1
DSP core should be shut down first to avoid clicks/pops.
2
The target/slew RAMs need to be written through the safeload registers. Safeload writes may be done in either single-write or burst-mode.
CONTROL PORT ADDRESSING
1.
Direct Read/Write. This method allows direct access to the
program and parameter RAMs. This mode of operation is
Table 12 shows the addressing of the AD1940's RAM and
normally used during a complete new load of the RAMs,
register spaces. The address space encompasses a set of registers
using burst-mode addressing. The clear registers bit in the
and three RAMs: one each for holding signal processing
core control register should be set to 0 using this mode to
parameters, holding the program instructions, and ramping
avoid any clicks or pops in the outputs. Note that it is also
parameter values. The program and parameter RAMs are
possible to use this mode during live program execution,
initialized on power-up from on-board boot ROMs.
but since there is no handshaking between the core and the
Table 13 shows the sizes and available writing modes of the
control port, the parameter RAM will be unavailable to the
parameter, program, and target/slew RAMs.
DSP core during control writes, resulting in clicks and pops
in the audio stream.
PARAMETER RAM CONTENTS
2.
Safeload Writes. Up to five safeload registers can be loaded
The parameter RAM is 28 bits wide and occupies Addresses 0 to
with address/data intended for the parameter RAM. The
1023. The parameter RAM is initialized to all 0s on power-up.
data is then transferred to the requested address when the
The data format of the parameter RAM is twos complement
RAM is not busy. This method can be used for dynamic
5.23. This means that the coefficients may range from +16.0
updates while live program material is playing through the
(minus 1