Ij

a
PLL/Multibit - DAC
AD1958
FEATURES
Flexible Serial Data Port with Right-Justified, Left-
5 V Stereo Audio DAC System
Justified, I2S-Compatible, and DSP Serial Port Modes
Accepts 16-/18-/20-/24-Bit Data
28-Lead SSOP Plastic Package
Supports 24 Bits, 192 kHz Sample Rate
APPLICATIONS
Accepts a Wide Range of Sample Rates Including:
DVD, CD, Home Theater Systems, Automotive Audio
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz
Systems, Sampling Musical Keyboards, Digital Mixing
Multibit Sigma-Delta Modulator with "Perfect Differential
Consoles, Digital Audio Effects Processors
Linearity Restoration" for Reduced Idle Tones and
Noise Floor
PRODUCT OVERVIEW
Data Directed Scrambling DAC--Least Sensitive to Jitter
The AD1958 is a complete high-performance single-chip stereo
Single-Ended Output for Easy Use
digital audio playback system. It is comprised of a multibit sigma-
108 dB Signal-to-Noise (Not Muted) at 48 kHz Sample
delta modulator, digital interpolation filters, and analog output
Rate (A-Weighted Stereo)
drive circuitry with an on-board dual PLL clock generator.
109 dB Dynamic Range (Not Muted) at 48 kHz Sample
Other features include an on-chip stereo attenuator and mute,
Rate (A-Weighted Stereo)
programmed through an SPI-compatible serial control port.
?96 dB THD + N (Stereo)
The AD1958 is fully compatible with all known DVD formats
75 dB Stop Band Attenuation
including 96 kHz and 192 kHz sample frequencies and 24 bits.
On-Chip Clickless Volume Control
It also is backwards-compatible by supporting 50 ?s/15 ?s
Hardware and Software Controllable Clickless Mute
digital de-emphasis for "redbook" compact discs, as well as
Serial (SPI) Control for: Serial Mode, Number of Bits,
de-emphasis at 32 kHz and 48 kHz sample rates.
Sample Rate, Volume, Mute, De-Emphasis
The AD1958 has a simple but flexible serial data input port that
Digital De-Emphasis Processing for 32 kHz, 44.1 kHz,
allows for glueless interconnection to a variety of ADCs, DSP
and 48 kHz Sample Rates
chips, AES/EBU receivers, and sample rate converters. The
Programmable Dual Fractional-N PLL Clock Generator
AD1958 can be configured in left-justified, I2S, right-justified,
27 MHz Master Clock Oscillator
or DSP serial-port-compatible modes. It can support 16, 20,
Better than 100 ps rms Master Clock Jitter
and 24 bits in all modes. The AD1958 accepts serial audio data
Generated System Clocks
in MSB first, two's-complement format, and operates from a
SCLK0: 33.8688 MHz
single 5 V power supply. It is fabricated on a single monolithic
SCLK1: 22.5792 MHz, 24.576 MHz, 33.8688 MHz, or
integrated circuit and housed in a 28-lead SSOP package for
36.864 MHz
operation over the temperature range ?40?C to +105?C.
SCLK2: 16.9344 MHz
FUNCTIONAL BLOCK DIAGRAM
LOOP
CLOCK
CONTROL DATA
FILTERS
OUTPUTS
INPUT
XIN
XOUT MCLK
2
3
3
AD1958
PLL
SERIAL CONTROL
VOLTAGE
OSC
CIRCUIT
INTERFACE
REFERENCE
MULTIBIT
8  fS
OUTPUT
ATTEN/MUTE
DAC
SIGMA-DELTA
L
BUFFER
INTERPOLATOR
MODULATOR
SERIAL
16-/20-/24-
ANALOG
DATA
BIT DIGITAL
OUTPUTS
INTERFACE
3
DATA INPUT
MULTIBIT
8  fS
OUTPUT
ATTEN/MUTE
R
DAC
SIGMA-DELTA
BUFFER
INTERPOLATOR
MODULATOR
2
2
3
RESET
MUTE
ZERO FLAG
PLL SUPPLY
DIGITAL SUPPLY
ANALOG SUPPLY
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
use, nor for any infringements of patents or other rights of third parties that
Tel: 781/329-4700
www.analog.com
may result from its use. No license is granted by implication or otherwise
Fax: 781/326-8703
? Analog Devices, Inc., 2001
under any patent or patent rights of Analog Devices.
AD1958?SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages
(AVDD, DVDD, PVDD)
5.0 V
25?C
Ambient Temperature
12.288 MHz (256 ?fS Mode)
Input Clock
Input Signal
996.0938 Hz,
0 dB Full Scale
Input Sample Rate
48 kHz
Measurement Bandwidth
20 Hz to 20 kHz
Word Width
24 Bits
Load Capacitance
100 pF
47 k
Load Impedance
Input Voltage HI
2.0 V
Input Voltage LO
0.8 V
ANALOG PERFORMANCE
Min
Typ
Max
Unit
Resolution
24
Bits
Signal-to-Noise Ratio (20 Hz to 20 kHz)
No Filter (Stereo)
105
dB
With A-Weighted Filter (Stereo)
108
dB
Dynamic Range (20 Hz to 20 kHz, ?60 dB Input)
No Filter (Stereo)
105
dB
With A-Weighted Filter (Stereo)
102
109
dB
Total Harmonic Distortion + Noise (Stereo)
?90
?96
dB
PLL Performance
Master Clock Input Frequency
27
MHz
Generated System Clocks
SCLK0
33.8688
MHz
SCLK1
12.288
MHz
SCLK2
22.5792
MHz
Jitter (SCLK0 and SCLK1)
110
175
ps rms
Jitter (MCLK)
60
100
ps rms
Duty Cycle (SCLK0, SCLK1)1
50
%
Duty Cycle (MCLK)
49
50
51
%
Analog Outputs
Single-Ended Output Range (? Full Scale)
3.17
V p-p
Output Capacitance at Each Output Pin
2
pF
Out-of-Band Energy (0.5 ?fS to 100 kHz)
?90
dB
VREF (FILTR)
2.39
V
DC Accuracy
? 2.0
Gain Error
?5
+5
%
? 0.015
Interchannel Gain Mismatch
?0.15
+0.15
dB
ppm/?C
Gain Drift
150
250
DC Offset
?25
?3
+20
mV
Interchannel Crosstalk (EIAJ Method)
?120
dB
? 0.1
Interchannel Phase Deviation
Degrees
Mute Attenuation
?100
dB
? 0.1
De-Emphasis Gain Error
dB
NOTES
1
In some combinations with Clock Configuration Mode = 1 (see Table III), SCLK will not be 50%.
2
Performance of right and left channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
DIGITAL I/O (?40?C to +105?C )
Min
Typ
Max
Unit
Input Voltage HI (VIH)
2.0
V
Input Voltage LO (VIL)
0.8
V
?A
Input Leakage (IIH @ VIH = 2.4 V)
10
?A
Input Leakage (IIL @ VIL = 0.8 V)
10
High Level Output Voltage (VOH) IOH = 1 mA
3.5
V
Low Level Output Voltage (VOL) IOL = 1 mA
0.4
V
Input Capacitance
20
pF
Specifications subject to change without notice.
REV. 0
?2?
AD1958
TEMPERATURE RANGE
Min
Typ
Max
Unit
?C
Specifications Guaranteed
25
?C
+105*
Functionality Guaranteed
?40
?C
Storage
?55
+125
NOTE
*105?C ambient guaranteed for a 4-layer board, two 1 oz. planes, two 2 oz. signal layers. Derate to 85 ?C for 2-layer board, 2 oz. layers.
Specifications subject to change without notice.
POWER
Min
Typ
Max
Unit
Supplies
Voltage, Analog Digital PLL
4.50
5
5.50
V
Analog Current
36
41
mA
Digital Current
25
29
mA
PLL Current
30
34
mA
Dissipation
Operation--All Supplies
455
540
mW
Operation--Analog Supply
180
mW
Operation--Digital Supply
125
mW
Operation--PLL Supply
150
mW
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
?60
dB
20 kHz 300 mV p-p Signal at Analog Supply Pins
?50
dB
Specifications subject to change without notice.
DIGITAL FILTER CHARACTERISTICS
Sample Rate (kHz)
Pass Band (kHz)
Stop Band (kHz)
Stop Band Attenuation (dB)
Pass Band Ripple (dB)
? 0.0002
44.1
DC?20
24.1?328.7
75
? 0.0002
48
DC?21.8
26.23?358.28
75
? 0.0005
96
DC?39.95
56.9?327.65
75
192
DC?87.2
117?327.65
60
0/?0.04 (DC?21.8 kHz)
0/?0.5 (DC?65.4 kHz)
0/?1.5 (DC?87.2 kHz)
Specifications subject to change without notice.
GROUP DELAY
Chip Mode
Group Delay Calculation
fS
Group Delay
Unit
INT8?Mode
?s
24.625/fS
48 kHz
513
?s
INT4?Mode
96 kHz
164
15.75/fS
INT2?Mode
?s
14/fS
192 kHz
72.91
Specifications subject to change without notice.
DIGITAL TIMING (Guaranteed over ?40?C to +105 C, AVDD = DVDD = PVDD = 5.0 V
10%)
Min
Unit
MCLK Period (FMCLK = 256 ?FLRCLK)
54
ns
tDMP
tDML
MCLK LO Pulsewidth (All Modes)
15
ns
tDMH
MCLK HI Pulsewidth (All Modes)
10
ns
BCLK HI Pulsewidth
20
ns
tDBH
tDBL
BCLK LO Pulsewidth
20
ns
tDBP
BCLK Period
60
ns
LRCLK Setup
20
ns
tDLS
tDLH
LRCLK Hold (DSP Serial Port Mode Only)
20
ns
tDDS
SDATA Setup
15
ns
SDATA Hold
15
ns
tDDH
tRSTL
RST LO Pulsewidth
15
ns
Specifications subject to change without notice.
?3?
REV. 0
AD1958
ABSOLUTE MAXIMUM RATINGS*
PACKAGE CHARACTERISTICS
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . ?0.3 V to +6 V
Min
Typ
Max
Unit
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . ?0.3 V to +6 V
JA (Thermal Resistance)
?C/W
109.0
Digital Inputs . . . . . . . . . . DGND ? 0.3 V to DVDD + 0.3 V
Junction-to-Ambient
Analog Inputs . . . . . . . . . . AGND ? 0.3 V to AVDD + 0.3 V
(2-Layer Board)
AGND to DGND . . . . . . . . . . . . . . . . . . . . ?0.3 V to + 0.3 V
?C/W
JA (Thermal Resistance)
78.58
Reference Voltage . . . . . . . . . . . . . . . . . . . . . (AVDD + 0.3)/2
Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300?C
Junction-to-Ambient
(4-Layer Board--
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
2 Signal, 2 Planes)
nent damage to the device. This is a stress rating only; functional operation of the
JA (Thermal Resistance)
device at these or any other conditions above those listed in the operational
?C/W
Junction-to-Case
39.0
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
WARNING!
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1958 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model
Temperature
Package Description
Package Option
?40?C to +105 ?C
28-Lead Small Outline Package
RS-28
AD1958YRS
?40?C to +105 ?C
AD1958YRSRL
28-Lead Small Outline Package
RS-28 on 13" Reels
EVAL-AD1958EB
Evaluation Board
PIN CONFIGURATION
CCLK 1
CDATA
28
CLATCH
MUTE
2
27
RESET 3
ZERO
26
LRCLK 4
FILTB
25
BCLK 5
24
AVDD
SDATA 6
OUTL
23
AD1958
DVDD 7
TOP VIEW  22 AGND1
DGND 8 (Not to Scale) 21 FLTR
SCLK0 9
OUTR
20
SCLK1 10
AGND0
19
SCLK2 11
LF1
18
MCLK 12
LF0
17
XOUT 13
PGND
16
XIN 14
PVDD
15
?4?
REV. 0
AD1958
PIN FUNCTION DESCRIPTIONS
Pin
Input/Output
Mnemonic
Description
1
I
CCLK
Control Clock Input for Control Data. Control input data must be valid on
the rising edge of CCLK. CCLK may be continuous or gated.
CLATCH
2
I
Latch Input for Control Data
RESET
3
I
Reset. The AD1958 is placed in a reset mode when this pin is held LO.
The serial control port registers are reset to their default values. Set HI for
normal operation.
4
I
LRCLK
Left/Right Clock Input for Input Data. Must run continuously.
5
I
BCLK
Bit Clock Input for Input Data. Need not run continuously; may be gated
or used in a burst fashion.
6
I
SDATA
Serial input, MSB first, containing two channels of 16/20/24 bits of two's-
complement data per channel.
7
I
DVDD
Digital Power Supply Connect to Digital 5 V Supply
8
I
DGND
Digital Ground
9
O
SCLK0
33.8688 MHz Clock Output
10
O
SCLK1
256/384/512/768 fS Output
11
O
SCLK2
16.9344 MHz/22.5792 MHz/512 fS Output
12
I/O
MCLK
27 MHz Master Clock Output/256 fS DAC Clock Input
13
O
XOUT
27 MHz Crystal Oscillator Output
14
I
XIN
27 MHz Crystal Oscillator/External Clock Input
15
PVDD
PLL Power Supply. Connect to PLL 5 V Supply.
16
PGND
PLL Ground
17
LF0
PLL0 Loop Filter
18
LF1
PLL1 Loop Filter
19
AGND0
Analog Ground
20
O
OUTR
Right Channel Positive Line Level Analog Output
21
O
FILTR
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10 ?F and 0.1 ?F capacitors to AGND.
22
I
AGND1
Analog Ground
23
O
OUTL
Left Channel Line Level Analog Output
24
AVDD
Analog Power Supply. Connect to Analog 5 V Supply.
Filter Capacitor Connection. Connect 10 ?F Capacitor to AGND.
25
FILTB
26
O
ZERO
Zero Flag Output. This pin goes HI when both channels have zero signal
input for more than 1024 L/R Clock Cycles.
27
I
MUTE
Mute. Assert HI to Mute Both Stereo Analog Outputs. Deassert LO for
normal operation.
28
I
CDATA
Serial Control Input, MSB first, containing 16 bits of unsigned data
per channel. Used for specifying channel-specific attenuation and mute.
into the audio band; care should be exercised in selecting
FUNCTIONAL DESCRIPTION
these components.
DAC
The AD1958 has two DAC channels arranged as a stereo pair
The FILTB and FILTR pins should be bypassed by external
with single-ended analog outputs. Each channel has its own
capacitors to ground. The FILTB pin is used to reduce the noise
independently programmable attenuator, adjustable in 16384
of the internal DAC bias circuitry, thereby reducing the DAC
linear steps. Digital inputs are supplied through a serial data
output noise. The voltage at the VREF pin, FILTR (VREF ~ 2.39 V)
input pin, SDATA, a frame clock, LRCLK, and a bit clock, BLCK.
can be used to bias external op amps used to filter the output signals.
Each analog output pin sits at a dc level of VREF (present at
The DAC master clock frequency is 256 fS for the 32 kHz?48 kHz
FILTR), and swings ? 1.585 V for a 0 dB digital input signal.
i
range (8  interpolation, see Table I). For the 96 kHz range (4
A single op amp third-order external low-pass filter is recom-
nterpolation) this is 128 fS. At 192 kHz (2  interpolation), this
mended to remove high-frequency noise present on the output
is 64 fS. It is supplied internally from the PLL clock system when
pins. The output phase can be changed in an SPI control
MCLK mode is set to Output in the PLL Control Register.
register to accommodate inverting and noninverting filters.
When the MCLK mode is changed to Input, it must be supplied
Note that the use of op amps with low slew rate or low band-
from an external source connected to MCLK. The output from
width may cause high frequency noise and tones to fold down
the 27 MHz PLL clock is disabled in this case.
REV. 0
?5?
AD1958
Table I. DAC Control Register
Bit 11:10
Bit 9:8
Bit 7
Bit 6
Bit 5:4
Bit 3:2
Bit 1:0
Interpolation
Serial Data
Serial Data
De-Emphasis
SPI Register
Factor
Width
Output Phase
Soft Mute
Format
Filter
Address
00 = 8?/font>*
00 = I2S*
00 = 24 Bits*
0 = Noninverted*
0 = No Mute*
00 = None*
01
01 = 4?/font>
01 = 20 Bits
1 = Inverted
1 = Muted
00 = Right Justified
01 = 44.1 kHz
10 = 2?/font>
10 = 16 Bits
10 = DSP
10 = 32 kHz
11 = 48 kHz
11 = Not Allowed
11 = 16 Bits
11 = Left Justified
*Default Setting
PLL CLOCK SYSTEM
Table II. DAC Volume Registers
The PLL clock system is expected to be run from a 27 MHz
Bit 15:2
Bit 1:0
master clock supplied by the on-board crystal oscillator or an
external source connected to XIN. With the MCLK mode set
Volume
SPI Register Address
to Output, the 27 MHz clock is buffered out to the MCLK
14 Bits, Unsigned
00 = Left Volume
pin. When set to Input, this pin is the 256 fS master clock input
14 Bits, Unsigned
10 = Right Volume
for the DAC. SCLK0 is always set to 33.8688 MHz. SCLK1 is
Default is full volume
intended to be used as a master audio clock and will be a multiple
of the sample rate set in the PLL control register (see Table III).
RESET/POWER-DOWN
In Mode 0 (Bit 8), it can be set to 512 or 768 times either
RESET will set the control registers to their default settings. The
4
44.1 kHz or 48 kHz. SCLK2 will be 16.3944 MHz (384
chip should be reset on power-up. After reset is deasserted, the
4.1 kHz). In Mode 1, SCLK1 can be set to 256, 384, 512,
part will come out of reset on the next rising LRCLK.
or 768 times 32 kHz, 44.1 kHz, or 48 kHz. SCLK2 can be
SERIAL CONTROL PORT
set to a constant 22.5792 MHz (512  44.1 kHz) or 512 fS.
The AD1958 has an SPI-compatible control port to permit
There are two loop filter pins, LF0 and LF1. They should each
programming the internal control registers for the PLL and DAC.
be bypassed to PVDD by a network consisting of a 33 nF capaci-
The DAC output levels may be independently programmed
tor in series with a 750 resistor, paralleled with a 1.8 nF capacitor.
by means of an internal digital attenuator adjustable in 16384
The 27 MHz Master Clock oscillator should have a crystal cut for
linear steps.
an 18 pF load connected between XIN and XOUT, with 22 pF
capacitors connected from XIN and XOUT to PGND.
Table III. PLL Control Register
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7:6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1:0
PLL2
PLL1
XTAL
SPI
Power-
Power-
Power-
Clock
SCLK1
Frequency
SCLK2
MCLK
Register
Double2
Down
Down
Down
Configuration
fS
Select
Select
Mode
Address
0 = On1
0 = On1
0 = On1
0 = Mode 01
0 = Output1 11
SCLK1 =
Reserved
Reserved
000: 36.864 MHz1
1 = PD
1 = PD
1 = PD
Set to 0
Set to 0
1 = Input
100: 24.576 MHz
110: 33.8688 MHz
111: 22.5792 MHz
Other combinations reserved
SCLK2 = 16.9344 MHz
0 = 256 fS
0 = Normal  0 = 22.5792 MHz
1 = Mode 1
00 = 48 kHz
1 = 512  fS2
1 = 384 fS
1=
01 = Not
Allowed
fNOMINAL  2
10 = 32 kHz
11 = 44.1 kHz
NOTES
1
Default Setting
2
In Mode 1, Frequency Double affects SCLK1 always and SCLK2 in 512
fS mode.
?6?
REV. 0
AD1958
is expected that the digital and PLL sections will be run from a
The SPI control port is a 3-wire serial control port. The format
common supply but isolated from one another. It is important
is similar to the Motorola SPI format except the input data word
that the analog supply be as clean as possible.
is 16 bits wide. Max serial bit clock frequency is 8 MHz and
may be completely asynchronous to the PLL system or the
The internal voltage reference is brought out on Pin 21 (FILTR)
DAC. Figure 1 shows the format of the SPI signal. Note that
and should be bypassed as close as possible to the chip with a
the CCLK can be gated or continuous, CLATCH should be
parallel combination of 10 ?F and 100 nF. The reference volt-
low during the 16 active clocks.
age may be used to bias external op amps to the common-mode
voltage of the analog output signal pins. The current drawn
POWER SUPPLY AND VOLTAGE REFERENCE
from the FILTR pin should be limited to less than 50 ?A.
The AD1958 is designed for five-volt supplies. Separate power
supply pins are provided for the analog, digital, and PLL sec-
SERIAL DATA PORTS--DATA FORMAT
tions. These pins should be bypassed with 100 nF ceramic
The DAC serial data input mode defaults to I2S. By changing
chip capacitors, as close to the pins as possible, to minimize
Bits 4 and 5 in the DAC control register, the mode can be
noise. A bulk aluminum electrolytic capacitor of at least 22 ?F
changed to RJ, DSP, or LJ. The word width defaults to 24 bits
should also be provided on the same PC board. For best perfor-
but can be changed by programming Bits 8 and 9 in the DAC
mance it is recommended that the analog supply be separate
Control Register.
from the digital and PLL supply. It is recommended that all
Figure 2 shows the serial mode formats.
supplies be isolated by ferrite beads in series with each supply. It
CLATCH
CCLK
D0
D15
D14
CDATA
Figure 1. Format of SPI Signal
RIGHT CHANNEL
LRCLK
LEFT CHANNEL
BCLK
MSB
LSB
SDATA
MSB
LSB
LEFT-JUSTIFIED MODE--16 TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
MSB
LSB
MSB
LSB
SDATA
12S MODE--16 TO 24 BITS PER CHANNEL
RIGHT CHANNEL
LRCLK
LEFT CHANNEL
BCLK
SDATA
LSB
LSB
MSB
MSB
RIGHT-JUSTIFIED MODE--SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
SDATA
LSB
MSB
LSB
MSB
DSP MODE--16 TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2  fS.
3. BCLK FREQUENCY IS NORMALLY 64  LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 2. Stereo Serial Modes
REV. 0
?7?
AD1958
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Small Outline Package (SSOP)
(RS-28)
0.407 (10.34)
0.397 (10.08)
28
15
0.212 (5.38)
0.205 (5.21)
0.311 (7.9)
PIN 1
0.301 (7.64)
14
1
0.078 (1.98)
0.07 (1.79)
0.068 (1.73)
0.066 (1.67)
0
8
0.03 (0.762)
0.008 (0.203) 0.0256
0.015 (0.38)
SEATING
0.022 (0.558)
0.009 (0.229)
(0.65)
0.010 (0.25)
PLANE
0.002 (0.050)  BSC
0.005 (0.127)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
?8?
REV. 0