Ij

a
Nonvolatile Memory,
1024-Position Digital Potentiometers
AD5231*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Nonvolatile Memory1 Preset Maintains Wiper Settings
1024-Position Resolution
AD5231
CS
VDD
Full Monotonic Operation
RDAC
ADDR
10 k , 50 k , and 100 k  Terminal Resistance
RDAC
CLK
REGISTER
DECODE
A
SDI
SDI
Permanent Memory Write-Protection
W
Wiper Settings Read Back
SERIAL
INTERFACE
EEMEM1
GND
B
Linear Increment/Decrement
Log Taper Increment/Decrement
Push Button Increment/Decrement Compatible
SDO
SDO
DIGITAL
O1
REGISTER
SPI Compatible Serial Interface with Readback Function
2
WP
DIGITAL
EEMEM
O2
3 V to 5 V Single Supply or  2.5 V Dual Supply
OUTPUT
CONTROL
BUFFER
RDY
28 Bytes User Nonvolatile Memory for Constant Storage
EEMEM2
100 Year Typical Data Retention TA = 55 C
VSS
28 BYTES
USER EEMEM
APPLICATIONS
PR
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage to Current Conversion
100
Programmable Filters, Delays, Time Constants
RWA
RWB
Line Impedance Matching
Power Supply Adjustment
75
Low Resolution DAC Replacement
GENERAL DESCRIPTION
50
The AD5231 provides nonvolatile memory digitally controlled
potentiometers2 with 1024-position resolution. These devices
perform the same electronic adjustment function as a mechanical
25
potentiometer. The AD5231's versatile programming via a stan-
dard 3-wire serial interface allows 16 modes of operation and
adjustment, including scratch pad programming, memory stor-
0
ing and retrieving, increment/decrement, log taper adjustment,
512
768
0
256
1023
wiper setting read back, and extra user-defined EEMEM.
CODE ? Decimal
In the scratch pad programming mode, a specific setting can be
Figure 1. RWA(D) and RWB(D) vs. Decimal Code
programmed directly to the RDAC2 register, which sets the resis-
Other operations include linear step increment and decrement
tance at terminals W-A and W-B. The RDAC register can also
commands such that the setting in the RDAC register can be
be loaded with a value previously stored in the EEMEM1 regis-
moved UP or DOWN, one step at a time. For logarithmic changes
ter. The value in the EEMEM can be changed or protected.
in wiper setting, a left/right bit shift command adjusts the level
When changes are made to the RDAC register, the value of the
in ? 6 dB steps.
new setting can be saved into the EEMEM. Thereafter, such value
will be transferred automatically to the RDAC register during
The AD5231 is available in thin TSSOP-16 package. All parts
system power ON. It is enabled by the internal preset strobe.
are guaranteed to operate over the extended industrial tempera-
ture range of ?40?C to +85?C.
EEMEM can also be retrieved through direct programming and
external preset pin control.
NOTES
1
The terms Nonvolatile Memory and EEMEM are used interchangeably.
2
The terms Digital Potentiometer and RDAC are used interchangeably.
*Patent pending
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
use, nor for any infringements of patents or other rights of third parties that
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may result from its use. No license is granted by implication or otherwise
Fax: 781/326-8703
? Analog Devices, Inc., 2001
under any patent or patent rights of Analog Devices.
AD5231?SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 10 k , 50 k , 100 k
VERSIONS
10% and VSS = 0 V, VA = +VDD, VB = 0 V, ?40 C < TA < +85 C, unless otherwise noted.)
(VDD = 3 V
10% or 5 V
Typ1
Parameter
Symbol
Conditions
Min
Max
Unit
DC CHARACTERISTICS
RHEOSTAT MODE
? 1/2
Resistor Differential Nonlinearity2
R-DNL
RWB, VA = NC, Monotonic
?1
+1.8
LSB
Resistor Integral Nonlinearity2
R-INL
RWB, VA = NC
?0.2
+0.2
% FS
RWB
D = 3FFH
?40
+20
%
Nominal Resistor Tolerance
RAB/ T
ppm/?C
600
Resistance Temperature Coefficient
IW = 100 ?A, VDD = 5.5 V,
15
100
Wiper Resistance
RW
Code = Half-Scale
IW = 100 ?A, VDD = 3 V,
50
Code = Half-Scale
DC CHARACTERISTICS
POTENTIOMETER DIVIDER MODE
Resolution
N
10
Bits
Monotonic, TA = 25?C
? 1/2
Differential Nonlinearity3
DNL
?1
+1
LSB
Monotonic, TA = ?40?C or +85?C
?1
+1.25
LSB
Integral Nonlinearity3
INL
?0.4
+0.4
% FS
VW/ T
ppm/?C
Voltage Divider Temperature Coefficient
Code = Half-Scale
15
Code = Full-Scale
?3
0
% FS
Full-Scale Error
VWFSE
Code = Zero-Scale
0
+1.5
% FS
Zero-Scale Error
VWZSE
RESISTOR TERMINALS
Terminal Voltage Range4
VA, B, W
VSS
VDD
V
Capacitance5 A, B
CA, B
f = 1 MHz, Measured to GND,
50
pF
Code = Half-Scale
Capacitance5 W
CW
f = 1 MHz, Measured to GND,
50
pF
Code = Half-Scale
?A
Common-Mode Leakage Current5, 6
ICM
VW = VDD/2
0.01
1
DIGITAL INPUTS and OUTPUTS
With Respect to GND, VDD = 5 V
2.4
V
Input Logic High
VIH
With Respect to GND, VDD = 5 V
0.8
V
Input Logic Low
VIL
With Respect to GND, VDD = 3 V
2.1
V
Input Logic High
VIH
With Respect to GND, VDD = 3 V
0.6
V
Input Logic Low
VIL
With Respect to GND,
Input Logic High
VIH
VDD = +2.5 V, VSS = ?2.5 V
2.0
V
With Respect to GND,
Input Logic Low
VIL
VDD = +2.5 V, VSS = ?2.5 V
0.5
V
RPULL-UP = 2.2 kto 5 V
4.9
V
Output Logic High (SDO, RDY)
VOH
IOL = 1.6 mA, VLOGIC = 5 V
0.4
V
Output Logic Low
VOL
? 2.5
?A
VIN = 0 V or VDD
Input Current
IIL
Input Capacitance5
CIL
4
pF
VDD = 5 V, VSS = 0 V, TA = 25?C
Output Current5
IO1, IO2
50
mA
VDD = 2.5 V, VSS = 0 V, TA = 25?C
7
mA
POWER SUPPLIES
VSS = 0 V
2.7
5.5
V
Single-Supply Power Range
VDD
? 2.25
? 2.75
VDD/VSS
V
Dual-Supply Power Range
?A
VIH = VDD or VIL = GND
2.7
10
Positive Supply Current
IDD
VIH = VDD or VIL = GND
40
mA
Programming Mode Current
IDD(PG)
Read Mode Current7
IDD(XFR)
VIH = VDD or VIL = GND
0.3
3
9
mA
VIH = VDD or VIL = GND,
Negative Supply Current
ISS
?A
VDD = +2.5 V, VSS = ?2.5 V
0.5
10
Power Dissipation8
PDISS
VIH = VDD or VIL = GND
0.018
0.05
mW
VDD = 5 V ? 10%
Power Supply Sensitivity5 IO IOL
PSS
0.002
0.01
%/%
DYNAMIC CHARACTERISTICS5, 9
?3 dB, R = 10 k/50 k/100 k
Bandwidth
BW
370/85/44
kHz
VA = 1 VRMS, VB = 0 V, f = 1 kHz,
Total Harmonic Distortion
THDW
RAB = 10 k
0.022
%
VA = 1 VRMS, VB = 0 V, f = 1 kHz,
Total Harmonic Distortion
THDW
RAB = 50 k, 100 k
0.045
%
?2?
REV. 0
AD5231
Typ1
Parameter
Symbol
Conditions
Min
Max
Unit
?s
VW Settling Time
tS
VA = VDD, VB = 0 V,
1.2/3.7/7
VW = 0.50% Error Band,
Code 000H to 200H
For RAB = 10 k/50 k/100 k
RWB = 5 k, f = 1 kHz
nV/Hz
Resistor Noise Voltage
eN_WB
9
NOTES
Typicals represent average readings at 25 C and VDD = 5 V.
1
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. I  W ~ 50 ?A @ VDD = +2.7 V and IW ~ 400 ?A @ VDD = +5 V for the RAB = 10 k
version, IW ~ 50 A for the RAB = 50 kand IW ~ 25 A for the RAB = 100 kversion. See test circuit Figure 12.
3
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V  A = VDD and VB = VSS. DNL
specification limits of ?1 LSB minimum are Guaranteed Monotonic operating conditions. See test circuit Figure 13.
4
Resistor terminals A, B, and W have no limitations on polarity with respect to each other. Dual Supply Operat ion enables ground-referenced bipolar signal adjustment.
5
Guaranteed by design and not subject to production test.
6
Common-mode leakage current is a measure of the dc leakage from any terminal B and W to a common-mode bias level of V DD/2.
7
Transfer (XFR) Mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 19.
8
PDISS is calculated from (IDD   VDD) + (ISS   VSS).
9
All dynamic characteristics use VDD = +2.5 V and VSS = ?2.5 V.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS 10 k , 50 k , 100 k
VERSIONS
(VDD = 3 V to 5.5 V and ?40 C < TA < +85 C, unless otherwise noted.)
Typ1
Parameter
Symbol
Conditions
Min
Max
Unit
INTERFACE TIMING
CHARACTERISTICS2, 3
Clock Cycle Time (tCYC)
t1
20
ns
CS Setup Time
10
ns
t2
CLK Shutdown Time to CS Rise
1
tCYC
t3
Input Clock Pulsewidth
t4, t5
Clock Level High or Low
10
ns
From Positive CLK Transition
5
ns
Data Setup Time
t6
From Positive CLK Transition
5
ns
Data Hold Time
t7
CS to SDO-SPI Line Acquire
40
ns
t8
CS to SDO-SPI Line Release
50
ns
t9
RP = 2.2 k, CL < 20 pF
CLK to SDO Propagation Delay4
t10
50
ns
RP = 2.2 k, CL < 20 pF
0
ns
CLK to SDO Data Hold Time
t11
CS High Pulsewidth5
t12
10
ns
CS High to CS High5
t13
4
tCYC
RDY Rise to CS Fall
t14
0
ns
CS Rise to RDY Fall Time
0.1
0.15
ms
t15
Read/Store to Nonvolatile EEMEM6
t16
Applies to Command 2H, 3H, 9H
25
ms
CS Rise to Clock Rise/Fall Setup
10
ms
t17
Not Shown in Timing Diagram
50
ms
Preset Pulsewidth (Asynchronous)
tPRW
PR Pulsed Low to Refreshed
Preset Response Time to RDY High
tPRESP
?s
Wiper Positions
70
FLASH/EE MEMORY RELIABILITY
Endurance7
100
K Cycles
Data Retention8
100
Years
NOTES
Typicals represent average readings at 25 C and VDD = 5 V.
1
2
Guaranteed by design and not subject to production test.
3
See timing diagram for location of measured values. All input control voltages are specified with t  R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level
of 1.5 V. Switching characteristics are measured using both VDD = 3 V and 5 V.
4
Propagation delay depends on value of VDD, RPULL_UP, and CL. See applications text.
5
Valid for commands that do not activate the RDY pin.
RDY pin low only for commands 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_8 ~ 1 s; CMD_9,10 ~0.12 s; CMD_2,3 ~20 s. Device operation at TA = ?40 C
6
and VDD < +3 V extends the save time to 35 s.
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at ?40 C, +25 C, and +85 C; typical endurance at 25 C is 700,000 cycles.
7
Retention lifetime equivalent at junction temperature (TJ) = 55 C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
8
will derate with junction temperature as shown in Figure 20 in the Flash/EE Memory Description section of this data sheet. The AD5231 contains 9,646 transistors.
Die size: 69 mil  115 mil, 7,993 sq. mil.
Specifications subject to change without notice.
?3?
REV. 0
AD5231
CPHA = 1
CS
t12
t13
t3
t1
t2
CLK
t5
CPOL = 1
t17
t4
t10
t11
t8
t9
MSB
LSB OUT
SDO
*
t7
t6
SDI
MSB
LSB
t14
t15
t16
RDY
*NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2a. CPHA = 1 Timing Diagram
CS
CPHA = 0
t12
t1
t3
t13
t2
t5
t17
CLK
t4
CPOL = 0
t8
t10
t11
t9
SDO
MSB OUT
LSB
*
t7
t6
LSB
SDI
MSB IN
t14
t15
t16
RDY
*NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2b. CPHA = 0 Timing Diagram
?4?
REV. 0
AD5231
Thermal Resistance Junction-to-Ambient JA,
ABSOLUTE MAXIMUM RATINGS1
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150?C/W
(TA = 25?C, unless otherwise noted)
Thermal Resistance Junction-to-Case JC,
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.3 V, +7 V
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28?C/W
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, ?7 V
Package Power Dissipation = (TJ Max ? TA)/ JA
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VA, VB, VW to GND . . . . . . . . . . . . . VSS ? 0.3 V, VDD + 0.3 V
NOTES
A?B, A?W, B?W
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? 20 mA
nent damage to the device. This is a stress rating; functional operation of the device
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? 2 mA
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
Digital Inputs and Output Voltage to GND
extended periods may affect device reliability.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.3 V, VDD + 0.3 V
2
Maximum terminal current is bounded by the maximum current handling of the
Operating Temperature Range3 . . . . . . . . . . . ?40?C to +85?C
switches, maximum power dissipation of the package, and maximum applied
Maximum Junction Temperature (TJ Max) . . . . . . . . . 150?C
voltage across any two of the A, B, and W terminals at a given resistance.
Storage Temperature . . . . . . . . . . . . . . . . . . ?65?C to +150?C
3
Includes programming of nonvolatile memory
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215?C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220?C
ORDERING GUIDE
RAB  Temperature Package
Package
Ordering
(k ) Range ( C)
Top Mark*
Model
Description  Option
Quantity
AD5231BRU10
10
?40 to +85
TSSOP-16
RU-16
96
5231B10
AD5231BRU10-REEL7
10
?40 to +85
TSSOP-16
RU-16
1,000
5231B10
AD5231BRU50
50
?40 to +85
TSSOP-16
RU-16
96
5231B50
AD5231BRU50-REEL7
50
?40 to +85
TSSOP-16
RU-16
1,000
5231B50
AD5231BRU100
100
?40 to +85
TSSOP-16
RU-16
96
5231BC
AD5231BRU100-REEL7
100
?40 to +85
TSSOP-16
RU-16
1,000
5231BC
*Line 1 contains ADI logo symbol and the date code YYWW; line 2 contains detail model number listed in this column.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
WARNING!
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5231 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.
REV. 0
?5?
AD5231
PIN CONFIGURATION
O1  1
16 O2
CLK  2
15 RDY
14 CS
SDI  3
AD5231   13 PR
SDO  4
TOP VIEW
GND  5 (Not to Scale) 12 WP
VSS  6
11 VDD
T  7
10 A
W
B  8
9
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
O1
Nonvolatile Digital Output #1. ADDR(O1) = 1H, data bit position D0
2
CLK
Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges.
3
SDI
Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.
4
SDO
Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 and 10
activate the SDO output. (See Instruction operation Truth Table, Table III.) Other commands shift out
the previously loaded SDI bit pattern delayed by 24 clock pulses. This allows daisy-chain operation of
multiple packages.
5
GND
Ground Pin, Logic Ground Reference
6
VSS
Negative Supply. Connect to zero volts for single supply applications.
7
T
Used as digital input during factory test mode. Connect to VDD or VSS.
8
B
B Terminal of RDAC
9
W
Wiper Terminal of RDAC. ADDR(RDAC1) = 0H.
10
A
A Terminal of RDAC1
11
VDD
Positive Power Supply Pin
WP
Write Protect Pin. When active low, WP prevents any changes to the present contents except PR and
12
cmd 1 and 8 will refresh the RDAC register from EEMEM. Execute on NOP instruction before returning
to WP high.
PR
13
Hardware Override Preset Pin. Refreshes the scratch pad register with current contents of the EEMEM
register. Factory default loads midscale 51210 until EEMEM loaded with a new value by the user (PR is
activated at the logic high transition).
CS
Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.
14
Ready. Active-high open drain output. Identifies completion of commands 2, 3, 8, 9, 10, and PR.
15
RDY
16
O2
Nonvolatile Digital Output #2. ADDR(O2) = 1H, data bit position D1.
?6?
REV. 0
Typical Performance Characteristics-- AD5231
1.5
2.0
VDD = 5V, VSS = 0V
TA = +85 C
1.5
1.0
TA = ?40 C
1.0
0.5
0.5
TA = +25 C
0
0
TA = +85 C T
?0.5
A = +25 C
TA = ?40 C
?1.0
?0.5
?1.5
?1.0
?2.0
128
384
640
896
1024
0
256
512
768
0
128
256
384
512
640
768
896
1024
CODE ? Decimal
CODE ? Decimal
TPC 4. R-DNL vs. Code, TA = ?40?C, +25?C, +85?C
TPC 1. INL vs. Code, TA = ?40?C, +25?C, +85?C Overlay,
Overlay, RAB = 10 k
RAB = 10 k
3000
2.0
VDD = 5.5V, V SS = 0V
VDD = 5V, VSS = 0V
TA = ?40 C TO +85 C
1.5
2500
1.0
TA = ?40 C
2000
0.5
1500
0
TA = +85 C
?0.5
1000
TA = +25 C
?1.0
500
?1.5
0
?2.0
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
CODE ? Decimal
CODE ? Decimal
RWB/ T vs. Code, RAB = 10 k
TPC 2. DNL vs. Code, TA = ?40?C, +25?C, +85?C Overlay,
TPC 5.
RAB = 10 k
1.0
100
VDD = 5V, VSS = 0V
VDD = 5.5V, V SS = 0V
TA = ?40 C TO +85 C
80
VB = 0V
0.5
VA = 2.00V
60
TA = +85 C
0
40
TA = +25 C
20
?0.5
0
TA = ?40 C
?1.0
?20
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
CODE ? Decimal
CODE ? Decimal
TPC 3. R-INL vs. Code, TA = ?40?C, +25?C, +85?C
RWB/ T vs. Code, RAB = 10 k
TPC 6.
Overlay, RAB = 10 k
REV. 0
?7?
AD5231
2
60
f?3dB = 370kHz, RAB = 10k
VDD = 2.7V, V SS = 0V
TA = 25 C
0
50
?2
?4
40
f?3dB = 44kHz, R = 100k
?6
30
f?3dB = 85kHz, RAB = 50k
?8
?10
20
?12
10
VA = 1mV rms
?14
VDD / V SS =  2.5V
D = MIDSCALE
?16
0
100k
1M
1k
10k
0
128
256
384
512
640
768
896
1024
FREQUENCY ? Hz
CODE ? Decimal
TPC 7. Wiper-On Resistance vs. Code
TPC 10. ?3 Bandwidth vs. Resistance. Test Circuit in
Figure 16.
0.12
4
DD/VSS =  2.5V
VA = 1V rms
0.10
3
IDD @ V DD/VSS = 5V/0V
0.08
2
.06
1
RA1 = 10k
B
0.04
ISS @ V DD/VSS = 5V/0V
0
0.02
50k
0
IDD @ V DD/VSS = 2.7V/0V
V
00k
ISS @ V DD/VSS = 2.7V/0V
0.00
?1
0.01
100
0.1
1
10
?40
?20
0
20
40
60
80
100
FREQUENCY ? kHz
TEMPERATURE ? C
TPC 8. IDD vs. Temperature, RAB = 10 k
TPC 11. Total Harmonic Distortion vs. Frequency
0.25
0
CODE = 200H
VDD = 5V
?5
VSS = 0V
100H
0.20
?10
?15
80H
?20
0.15
40H
FULL-SCALE
?25
20H
?30
0.10
10H
?35
08H
ZERO-SCALE
?40
0.05
MIDSCALE
?45
04H 02H 01H
?50
0.00
1k
10M
10k
100k
1M
0
2
4
6
8
10
12
FREQUENCY? Hz
CLOCK FREQUENCY ? MHz
TPC 9. IDD vs. Clock Frequency, RAB = 10 k
TPC 12. Gain vs. Frequency vs. Code, RAB = 10 k.
Test Circuit in Figure 18
?8?
REV. 0
AD5231
0
CODE = 200H
?10
100H
80H
100
VDD
90
?20
40H
20H
VW
?30
10H
EXPECTED
VALUE
08H
?40
MIDSCALE
04H
0.5V/DIV
100 s/DIV
10
02H
0%
?50
01H
?60
1k
10k
100k
1M
FREQUENCY ? Hz
TPC 13. Gain vs. Frequency vs. Code, RAB = 50 k.
TPC 16. Power-On Reset, VDD = 2.25 V,
Test Circuit in Figure 18
Code = 1010101010B
2.55
0
VDD/VSS = 5V/0V
CODE = 200H
CODE = 200H TO 1FFH
?10
100H
2.53
80H
?20
40H
R
2.51
RAB = 10k
20H
RAB = 50k
?30
T
= 100k
10H
AB
2.49
08H
?40
04H
2.47
02H
?50
01H
2.45
?60
0
5
10
15
20
25
10k
100k
1M
1k
TIME ? s
FREQUENCY ? Hz
TPC 14. Gain vs. Frequency vs. Code, RAB = 100 k.
PC 17. Midscale Glitch Energy, Code 200H to 1FFH
Test Circuit in Figure 18
80
ABF 100k
=
70
5V/DIV
R
AB = 50k
CS
60
R
RAB = 10k
50
CLK
40
5V/DIV
30
SDI
5V/DIV
20
IDD
VDD = +5.0V  100mV AC
20mA/DIV
10
VSS = 0V, VA = 5V, VB = 0V
MEASURED AT VW WITH CODE = 200 H
4ms/DIV
0
100
1k
10k
100k
1M
10M
REQUENCY ? Hz
TPC 15. PSRR vs. Frequency
TPC 18. IDD vs. Time (Save) Program Mode
REV. 0
?9?
AD5231
100
VA = VB = OPEN
5V/DIV
TA = 25 C
CS
10
CLK
R
RAB = 10k
5V/DIV
1
SDI
RAB = 50k
5V/DIV
0.1
IDD*
8
= 100k
2mA/DIV
AB
4ms/DIV
0.01
* SUPPLY CURRENT RETURNS TO MINIMUM POWER CONSUMPTION
1024
0
128
256
384
512
640
768
96
IF INSTRUCTION #0 (NOP) IS EXECUTED IMMEDIATELY AFTER
INSTRUCTION #1 (READ EEMEM)
CODE ? Decimal
TPC 19. IDD vs. Time (Read) Program Mode
TPC 20. IWB_MAX vs. Code
OPERATIONAL OVERVIEW
Scratch Pad and EEMEM Programming
The AD5231 digital potentiometer is designed to operate as a
The scratch pad register (RDAC register) directly controls the
true variable resistor replacement device for analog signals that
position of the digital potentiometer wiper. When the scratch
remain within the terminal voltage range of VSS < VTERM < VDD.
pad register is loaded with all zeros, the wiper will be connected
The basic voltage range is limited to a |VDD ? VSS| < 5.5 V. The
to the B-Terminal of the variable resistor. When the scratch pad
digital potentiometer wiper position is determined by the RDAC
register is loaded with midscale code (1/2 of full-scale position),
register contents. The RDAC register acts as a scratch pad regis-
the wiper will be connected to the middle of the variable resistor.
And when the scratch pad is loaded with full-scale code, all ones,
ter allowing as many value changes as necessary to place the
the wiper will connect to the A-Terminal. Since the scratch pad
potentiometer wiper in the correct position. The scratch pad
register is a standard logic register, there is no restriction on the
register can be programmed with any position value using the
number of changes allowed. The EEMEM registers have a program
standard SPI serial interface mode by loading the complete repre-
erase/write cycle limitation described in the Flash/EEMEM
sentative data word. Once a desirable position is found this value
Reliability section.
can be saved into an EEMEM register. Thereafter the wiper
position will always be set at that position for any future ON-
Basic Operation
OFF-ON power supply sequence. The EEMEM save process
The basic mode of setting the variable resistor wiper position
takes approximately 25 ms, during this time the shift register is
(programming the scratch pad register) is accomplished by
locked preventing any changes from taking place. The RDY pin
loading the serial data input register with the command instruc-
indicates the completion of this EEMEM save.
tion #11, which includes the desired wiper position data. When
There are 16 instructions that facilitate users' programming
the desired wiper position is found, the user would load the
serial data input register with the command instruction #2,
needs. Refer to Table III. The instructions are:
which makes a copy of the desired wiper position data into the
1. Do Nothing
nonvolatile EEMEM register. After 25 ms the wiper position
2. Restore EEMEM Setting to RDAC
will be permanently stored in the nonvolatile EEMEM location.
3. Save RDAC Setting to EEMEM
Table I provides an application-programming example listing
the sequence of serial data input (SDI) words and the serial data
4. Save RDAC Setting or User Data to EEMEM
output appearing at the SDO Pin in hexadecimal format.
5. Decrement 6 dB
6. Decrement 6 dB
Table I. Set and Save RDAC Data to EEMEM Register
7. Decrement One Step
SDI
SDO
Action
8. Decrement One Step
B00100H
XXXXXXH
Loads data 100H into RDAC
9. Reset EEMEM setting to RDAC
register, Wiper W moves to 1/4
10. Read EEMEM to SDO
full-scale position.
20XXXXH  B00100H
Saves copy of RDAC register
11. Read Wiper Setting to SDO
contents into EEMEM register.
12. Write Data to RDAC
13. Increment 6 dB
At system power ON, the scratch pad register is automatically
14. Increment 6 dB
refreshed with the value last saved in the EEMEM register. The
factory preset EEMEM value is midscale but thereafter, the
15. Increment One Step
EEMEM value can be changed by user.
16. Increment One Step
?10?
REV. 0
AD5231
During operation, the scratch pad (wiper) register can also be
VDD
refreshed with the current content of the nonvolatile EEMEM
register under hardware control by pulsing the PR Pin without
activating instruction 1 or 8. Beware that the PR pulse first sets
INPUT
F
300
the wiper at midscale when brought to logic zero, and then on
LOGIC
PINS
the positive transition to logic high, it reloads the RDAC wiper
register with the contents of EEMEM. Many additional advanced
programming commands are available to simplify the variable
resistor adjustment process, See Table III. For example, the
wiper position can be changed one step at a time by using the
GND
Increment/Decrement instruction or by 6 dB at a time with the
igure 4a. Equivalent ESD Digital Input Protection
Shift Left/Right instruction command. Once an Increment, Decre-
ment, or Shift command has been loaded into the shift register,
VDD
subsequent CS strobes will repeat this command. This is useful
for push button control applications. See the advanced control
modes section following the Instruction Operation Truth Table. A
INPUT
W
serial data output SDO Pin is available for daisy-chaining and
300
P
for readout of the internal register contents. The serial input
data register uses a 24-bit [instruction/address/data] WORD format.
EEMEM Protection
Write protect (WP) disables any changes of the scratch pad
GND
register contents regardless of the software commands, except
that the EEMEM setting can be refreshed and overwritten WP
Figure 4b. Equivalent WP Input Protection
by using commands 1, 8, and PR pulse. Therefore, the write-
Serial Data Interface
protect (WP) Pin provides a hardware EEMEM protection
The AD5231 contains a four-wire SPI compatible digital inter-
feature. To disable WP, it is recommended to execute a NOP
face (SDI, SDO, CS, and CLK). The AD5231 uses a 24-bit
command before returning WP to logic high.
serial data word loaded MSB first. The format of the SPI com-
Digital Input/Output Configuration
patible word is shown in Table II. The chip select CS Pin needs
All digital inputs are ESD-protected high-input impedance that
to be held low until the complete data word is loaded into the
can be driven directly from most digital sources. Active at logic
SDI Pin. When CS returns high the serial data word is decoded
low, PR and WP must be biased to VDD if they are not used. No
according to the instructions in Table III. The Command Bits
internal pull-up resistors are present on any digital input pins.
(Cx) control the operation of the digital potentiometer. The
The SDO and RDY Pins are open-drain digital outputs where
Address Bits (Ax) determine which register is activated. The
pull-up resistors are needed only if using these functions. A
Data Bits (Dx) are the values that are loaded into the decoded
resistor value in the range of 1 kto 10 kis a proper choice
register. Table V provides an address map of the EEMEM
which balances the power and switching speed trade off.
locations. The last instruction executed prior to a period of no
programming activity should be the No Operation (NOP) instruc-
The equivalent serial data input and output logic is shown in
tion. This will place the internal logic circuitry in a minimum power
Figure 3. The open drain output SDO is disabled whenever chip
select CS is logic high. ESD protection of the digital inputs is
dissipation state.
shown in Figures 4a and 4b.
The SPI interface can be used in two slave modes CPHA = 1,
CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to
PR
WP
the control bits, that dictate SPI timing in these MicroConverters?
and microprocessors: ADuC812/ADuC824, M68HC11, and
VALID
COMMAND
MC68HC16R1/916R1.
COMMAND
5V
PROCESSOR
AND ADDRESS
Daisy-Chain Operation
COUNTER
DECODE
The Serial Data Output Pin (SDO) serves two purposes. It can
RPULLUP
be used to readout the contents of the wiper setting and EEMEM
CLK
SERIAL
values using instructions 10 and 9, respectively. The remaining
REGISTER
instructions (#0?#8, #11?#15) are valid for daisy-chaining
SDO
multiple devices in simultaneous operations. Daisy-chaining
CS
GND
minimizes the number of port pins required from the controlling IC
AD5231
SDI
(see Figure 5). The SDO Pin contains an open drain N-Ch FET
that requires a pull-up resistor, if this function is used. As shown
Figure 3. Equivalent Digital Input-Output Logic
in Figure 5, users need to tie the SDO Pin of one package to the
MicroConverter is a registered trademark of Analog Devices Inc.
REV. 0
?11?
AD5231
SDI Pin of the next package. Users may need to increase the clock
Power-Up Sequence
period because the pull-up resistor and the capacitive loading at
Since there are diodes to limit the voltage compliance at terminals
the SDO-SDI interface may require additional time delay between
A, B, and W (see Figure 6), it is important to power VDD/VSS first
before applying any voltage to terminals A, B, and W. Otherwise,
subsequent packages. When two AD5231s are daisy-chained, 48
bits of data are required. The first 24 bits go to U2 and the second
the diode will be forward-biased such that VDD/VSS will be powered
24 bits go to U1. The 24 bits are formatted to contain the 4-bit
unintentionally and may affect the rest of the user's circuit. The
instruction, followed by the 4-bit address, 6-bit don't care, then
ideal power-up sequence is in the following order: GND, VDD, VSS,
the 10 bits of data. (The don't care can be used to store user
Digital Inputs, and V A/B/W. The order of powering VA, VB, VW,
information. See section Using Additional Internal Nonvolatile
and digital inputs are not important as long as they are powered
EEMEM). The CS should be kept low until all 48 bits are clocked
after VDD/VSS.
into their respective serial registers. The CS is then pulled high to
Regardless of the power-up sequence and the ramp rates of the
complete the operation.
power supplies, once VDD/VSS are powered, the power-on reset
remains effective, which retrieves EEMEM saved value to
+V
RDAC register.
AD5231
AD5231
Latched Digital Outputs
RP
C
2k
A pair of digital outputs, O1 and O2, is available on the AD5231
SDI
SDO
SDI
SDO
U1
U2
that provide a nonvolatile logic 0 or logic 1 setting. O1 and O2 are
standard CMOS logic outputs (shown in Figure 7). These outputs
CS
CS
are ideal to replace functions often provided by DIP switches. In
CLK
CLK
addition, they can be used to drive other standard CMOS logic
controlled parts that need an occasional setting change.
Figure 5. Daisy Chain Configuration using SDO
VDD
Terminal Voltage Operation Range