Ij

a
Nonvolatile Memory, Dual
1024-Position Digital Potentiometers
AD5235*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Dual, 1024-Position Resolution
25 k , 250 k  Nominal Resistance
AD5235
VDD
ADDR
Low Temperature Coefficient: 35 ppm/ C
RDAC1
DECODE
CS
REGISTER
Nonvolatile Memory1 Preset Maintains Wiper Settings
A1
CLK
W1
Permanent Memory Write-Protection
SERIAL
SDI
INTERFACE
B1
Wiper Settings Read Back
RDAC1
SDO
EEMEM1
Resistance Tolerance Stored in EEMEM1
POWER-ON
Linear Increment/Decrement
PR
PRESET
RDAC2
Log Taper Increment/Decrement
REGISTER
A2
SPI-Compatible Serial Interface
WP
EEMEM
W2
3 V to 5 V Single Supply or  2.5 V Dual Supply
CONTROL
RDY
B2
RDAC2
26 Bytes User Nonvolatile Memory for Constant Storage
EEMEM2
100-Year Typical Data Retention TA = 55 C
VSS
26 BYTES
USER EEMEM
APPLICATIONS
GND
SONET, SDH, ATM, Gigabit Ethernet
DWDM Laser Diode Driver, Optical Supervisory Systems
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
When changes are made to the RDAC register, the value of the
Programmable Voltage to Current Conversion
new setting can be saved into the EEMEM. Thereafter, it will be
Programmable Filters, Delays, Time Constants
transferred automatically to the RDAC register during system
Line Impedance Matching
power ON, which is enabled by the internal preset strobe. EEMEM
Power Supply Adjustment
can also be retrieved through direct programming and external
Low Resolution DAC Replacement
preset pin control.
The linear step increment and decrement commands cause the
GENERAL DESCRIPTION
The AD5235 provides a dual channel, digitally controlled digital
setting in the RDAC register to be moved UP or DOWN, one step
potentiometer2 with resolution of 1024 positions. These devices
at a time. For logarithmic changes in wiper setting, a left/right
bit shift command adjusts the level in ? 6 dB steps.
perform the same electronic adjustment function as a mechanical
potentiometer with enhanced resolution, solid-state reliability, and
The AD5235 is available in a thin TSSOP-16 package. All parts are
superior low temperature coefficient performance. The AD5235's
guaranteed to operate over the extended industrial temperature
versatile programming via a standard serial interface allows 16 modes
range of ?40?C to +85?C.
of operation and adjustment, including scratch pad programming,
memory storing and retrieving, increment/decrement, log taper adjust-
100
ment, wiper setting readback, and extra user-defined EEMEM.
Another key feature of the AD5235 is that the actual resistance
RWA
RWB
tolerance is stored in the EEMEM. The actual end-to-end resis-
75
tance can therefore be known, which is valuable for calibration,
tolerance matching and precision applications.
In the scratch pad programming mode, a specific setting can be
50
programmed directly to the RDAC2 register, which sets the resis-
tance between terminals W?A and W?B. The RDAC register can
also be loaded with a value previously stored in the EEMEM
25
register. The value in the EEMEM can be changed or protected.
*Patent pending
0
NOTES
0
256
1023
512
768
1
The terms nonvolatile memory and EEMEM are used interchangeably.
CODE ? Decimal
2
The terms digital potentiometer and RDAC are used interchangeably.
Figure 1. (D) and RWB(D) vs. Decimal Code
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
use, nor for any infringements of patents or other rights of third parties that
Tel: 781/329-4700
www.analog.com
may result from its use. No license is granted by implication or otherwise
Fax: 781/326-8703
? Analog Devices, Inc., 2002
under any patent or patent rights of Analog Devices.
AD5235?SPECIFICATIONS
ELECTRICAL CHARACTERISTICS, 25 k
AND 250 k
VERSIONS
(VDD = 3 V to 5.5 V, ?40 C < TA < +85 C, unless otherwise noted. )
1
Typ2
Parameter
Symbol
Conditions
Min
Max
Unit
DC CHARACTERISTICS?RHEOSTAT MODE Specifications Apply to All RDACs
Resistor Differential Nonlinearity3
R-DNL
RWB
?2
+2
LSB
3
R-INL
RWB
?4
+4
LSB
Resistor Integral Nonlinearity
RAB /T
ppm/ C
35
Resistance Temperature Coefficient
Wiper Resistance
RW
VDD = 5 V, IW = 1 V/RWB, Code = 200H
50
100
VDD = 3 V, IW = 1 V/RWB, Code = 200H
200
RWB /RWB
Ch 1 and 2 RWB, Dx = 3 FFH
0.1
%
Channel Resistance Matching
RWB
Nominal Resistor Tolerance
Dx = 3 FFH
?30
+30
%
DC CHARACTERISTICS?POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution
N
10
Bits
4
Differential Nonlinearity
DNL
?2
+2
LSB
4
INL
?4
+4
LSB
Integral Nonlinearity
Voltage Divider Temperature Coefficient VW /T
ppm/ C
Code = Half Scale
15
Full-Scale Error
VWFSE
Code = Full Scale
?6
0
LSB
Zero-Scale Error
VWZSE
Code = Zero Scale
0
4
LSB
RESISTOR TERMINALS
Terminal Voltage Range5
VA, B, W
VSS
VDD
V
Capacitance6 Ax, Bx
CA, B
f = 1 MHz, measured to GND,
11
pF
Code = Half Scale
Capacitance6 Wx
CW
f = 1 MHz, measured to GND,
80
pF
Code = Half Scale
?2
?A
Common-Mode Leakage Current6, 7
ICM
VW = VDD / 2
0.01
DIGITAL INPUTS AND OUTPUTS
With respect to GND, VDD = 5 V
2.4
V
Input Logic High
VIH
Input Logic Low
VIL
With respect to GND, VDD = 5 V
0.8
V
Input Logic High
VIH
With respect to GND, VDD = 3 V
2.1
V
With respect to GND, VDD = 3 V
0.6
V
Input Logic Low
VIL
Input Logic High
VIH
With respect to GND,
VDD = +2.5 V, VSS = ?2.5 V
2.0
V
With respect to GND,
Input Logic Low
VIL
VDD = +2.5 V, VSS = ?2.5 V
0.5
V
RPULL-UP = 2.2 kto 5 V
Output Logic High (SDO, RDY)
VOH
4.9
V
IOL = 1.6 mA, VLOGIC = 5 V
0.4
V
Output Logic Low
VOL
? 2.25
?A
Input Current
IIL
VIN = 0 V or VDD
Input Capacitance6
CIL
5
pF
POWER SUPPLIES
Single-Supply Power Range
VDD
VSS = 0V
3.0
5.5
V
? 2.25
? 2.75
VDD/VSS
V
Dual-Supply Power Range
VIH = VDD or VIL = GND, TA = 25 C
?A
Positive Supply Current
IDD
2
4.5
?A
Positive Supply Current
IDD
VIH = VDD or VIL = GND
3.5
6.0
VIH = VDD or VIL = GND
35
mA
Programming Mode Current
IDD(PG)
Read Mode Current8
IDD(XFR)
VIH = VDD or VIL = GND
0.3
3
9
mA
Negative Supply Current
ISS
VIH = VDD or VIL = GND,
?A
VDD = +2.5 V, VSS = ? 2.5 V
3.5
6.0
?W
9
Power Dissipation
PDISS
VIH = VDD or VIL = GND
18
50
VDD = 5 V ? 10%
Power Supply Sensitivity6
PSS
0.002
0.01
%/%
?2?
REV. A
AD5235
Min Typ2
Parameter
Symbol
Conditions
Max
Unit
DYNAMIC CHARACTERISTICS6, 10
VDD/VSS = ? 2.5 V, RAB = 25 k/250 k
Bandwidth ?3 dB
BW
125/12
kHz
VA = 1 Vrms, VB = 0 V, f =1 kHz
0.05
%
Total Harmonic Distortion
THDW
VW Settling Time
tS
VA = VDD, VB = 0 V, VW = 0.50% Error Band,
Code 000H to 200H, RAB = 25 k/250 k
?s
4/36
RAB = 25 k/250 k, TA = 25?C
nV/Hz
20/64
Resistor Noise Spectral Density
eN_WB
Crosstalk (CW1/CW2)
CT
VA = VDD, VB = 0 V, Measured VW1
with VW2 Making Full-Scale Change
90/21
nV?s
VDD = VA1 = +2.5 V, VSS = VB1 = ? 2.5 V,
Analog Crosstalk
CTA
Measure VW1 with VW2 = 5 V p-p
@ f = 1 kHz, Code 1 = 200H,
Code 2 = 3 FFH, RAB = 25 k/250 k
?81/?62
dB
INTERFACE TIMING CHARACTERISTICS Applies to All Parts6, 11
Clock Cycle Time (tCYC)
t1
20
ns
CS Setup Time
t2
10
ns
CLK Shutdown Time to CS Rise
1
tCYC
t3
Input Clock Pulsewidth
t4, t5
Clock Level High or Low
10
ns
Data Setup Time
t6
From Positive CLK Transition
5
ns
Data Hold Time
t7
From Positive CLK Transition
5
ns
CS to SDO-SPI Line Acquire
40
ns
t8
CS to SDO-SPI Line Release
t9
50
ns
RP = 2.2 k, CL < 20pF
12
CLK to SDO Propagation Delay
t10
50
ns
CS High Pulsewidth
13
t12
10
ns
CS High to CS High
13
t13
4
tCYC
RDY Rise to CS Fall
t14
0
ns
CS Rise to RDY Fall Time
0.15
0.3
ms
t15
14
Read/Store to Nonvolatile EEMEM
t16
Applies to Command 2H, 3H, 9H
30
ms
CS Rise to Clock Rise/Fall Setup
10
ns
t17
Preset Pulsewidth (Asynchronous)
tPRW
Not Shown in Timing Diagram
50
ns
PR Pulsed Low to Refreshed
Preset Response Time to
tPRESP
?s
Wiper Setting
Wiper Positions
140
FLASH/EE MEMORY RELIABILITY
Endurance15
100
K Cycles
Data Retention16
100
Years
NOTES
Parts can be operated at 2.7 V single supply, except from 0 C to ?40 C where minimum 3 V is needed.
1
Typicals represent average readings at 25 C and VDD = 5 V.
2
3
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. I  W ~ 50 mA for VDD = 2.7 V and IW ~ 400 mA for VDD = 5 V. See Test Circuit 1.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V  DD and VB = VSS.
DNL specification limits of ? 1 LSB maximum are guaranteed monotonic operating conditions. See Test Circuit 2.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other. Dual -supply operation enables ground referenced bipolar ac signal adjustment.
6
Guaranteed by design and not subject to production test.
7
Common-mode leakage current is a measure of the dc leakage from any terminal B and W to a common-mode bias level of V DD/2.
8
Transfer (XFR) mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 19.
9
PDISS is calculated from (IDD   VDD) + (ISS   VSS).
10
All dynamic characteristics use VDD = +2.5 V and VSS = ?2.5 V.
11
See Timing Diagrams for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from
a voltage level of 1.5 V. Switching characteristics are measured using both V  DD = 3 V and 5 V.
12
Propagation delay depends on value of VDD, RPULL_UP, and CL.
13
Valid for commands that do not activate the RDY pin.
RDY pin low only for commands 2, 3, 8, 9, 10, and PR software pulse: CHD_8 ~ 1 ms; CHD_9, 10 ~ 0.1 ms; CHD_2, 3 ~ 20 ms. Device operational at T A = ?40 C
14
and VDD < 3 V extends the save time to 35 ms.
Endurance is qualified to 100,000 cycles as per JEDEC Standard 22, Method A117 and measured at ?40 C, +25 C, and +85 C. Typical endurance at +25 C is
15
700,000 cycles.
Retention lifetime equivalent at junction temperature (T  J) = 55 C as per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of
16
0.6 V derates with junction temperature in the Flash/EE memory. See General Description section.
Specifications subject to change without notice.
The AD5235 contains 16,000 transistors. Die size: 99 mil  103 mil, 10,197 square mil.
?3?
REV. A
AD5235
TIMING DIAGRAMS
CS
CPHA = 1
t12
t13
t3
t1
t2
CLK
t5
CPOL = 1
t17
t4
t10
t11
t8
t9
MSB
LSB OUT
SDO
*
t7
t6
SDI
MSB
LSB
t14
t15
t16
RDY
*NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2a. CPHA = 1 Timing Diagram
CS
CPHA = 0
t12
t1
t3
t13
t2
t5
t17
CLK
t4
CPOL = 0
t8
t10
t11
t9
SDO
MSB OUT
LSB
*
t7
t6
LSB
SDI
MSB IN
t14
t15
t16
RDY
*NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2b. CPHA = 0 Timing Diagram
?4?
REV. A
AD5235
Thermal Resistance Junction-to-Ambient θJA
ABSOLUTE MAXIMUM RATINGS1
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150?C/W
(TA = 25?C, unless otherwise noted.)
Thermal Resistance Junction-to-Case θJC
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.3 V, +7 V
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28?C/W
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, ?7 V
Package Power Dissipation = (TJ MAX ? TA)/θJA
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
VA, VB, VW to GND . . . . . . . . . . . . . VSS ? 0.3 V, VDD + 0.3 V
NOTES
IA, IB, IW
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? 20 mA
nent damage to the device. This is a stress rating; functional operation of the device
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? 2 mA
at these or any other conditions above those listed in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
Digital Inputs and Output Voltage to GND . . ?0.3 V, VDD + 0.3 V
for extended periods may affect device reliability.
Operating Temperature Range3 . . . . . . . . . . . ?40?C to +85?C
2
Maximum terminal current is bounded by the maximum current handling of the
Maximum Junction Temperature (TJ MAX) . . . . . . . . . 150?C
switches, maximum power dissipation of the package, and maximum applied
Storage Temperature . . . . . . . . . . . . . . . . . . ?65?C to +150?C
voltage across any two of the A, B, and W terminals at a given resistance.
3
Includes programming of nonvolatile memory.
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215?C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220?C
ORDERING GUIDE
RWB_FS
Temperature Package
Package
Ordering
RDNL
Range (?C)
Top Mark*
Model
k
RINL
Description
Option
Quantity
?2
?4
AD5235BRU25
25
?40 to +85
TSSOP-16
RU-16
96
5235B25
?2
?4
AD5235BRU25-RL7
25
?40 to +85
TSSOP-16
RU-16
1,000
5235B25
?2
?4
AD5235BRU250
250
?40 to +85
TSSOP-16
RU-16
96
5235BD
?2
?4
AD5235BRU250-RL7
250
?40 to +85
TSSOP-16
RU-16
1,000
5235BD
AD5235EVAL25
25
1
AD5235EVAL250
250
1
*Line 1 contains ADI logo symbol and date code YYWW, line 2 branding contains differentiating detail by part type.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
WARNING!
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5235 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.
REV. A
?5?
AD5235
PIN CONFIGURATION
CLK  1
16 RDY
15 CS
SDI  2
14 PR
SDO  3
AD5235BRU
13 WP
GND  4
TOP VIEW
VSS  5
12 VDD
(Not To Scale)
A1 6
11 A2
W1  7
10 W2
B1  8
B2
9
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
CLK
Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges.
2
SDI
Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
3
SDO
Serial Data Output Pin. Open-drain output requires external pull-up resistor. CMD_9 and CMD_10 activate
the SDO output. See Table II, Command Operation Truth Table. Other commands shift out the previously
loaded SDI bit pattern delayed by 24 clock pulses. This allows daisy-chain operation of multiple packages.
4
GND
Ground Pin, Logic Ground Reference
5
VSS
Negative Supply. Connect to 0 V for single-supply applications.
6
A1
A Terminal of RDAC1
7
W1
Wiper Terminal of RDAC1. ADDR(RDAC1) = 0H.
8
B1
B Terminal of RDAC1
9
B2
B Terminal of RDAC2
10
W2
Wiper Terminal of RDAC2. ADDR(RDAC2) = 1H.
11
A2
A Terminal of RDAC2
12
VDD
Positive Power Supply Pin
WP
Write Protect Pin. When active low, WP prevents any changes to the present contents, except PR strobe.
13
CMD_1 and CMD_8 will refresh the RDAC register from EEMEM. Execute a NOP command before
returning to WP high.
PR
14
Hardware Override of Preset Pin. Refreshes the scratch pad register with current contents of the EEMEM
register. Factory default to midscale 51210 until EEMEM loaded with a new value by the user (PR is activated
at the logic high transition).
CS
Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.
15
Ready. Active-high open-drain output. Identifies completion of commands 2, 3, 8, 9, 10, and PR.
16
RDY
?6?
REV. A
Typical Performance Characteristics? AD5235
1.0
0.4
+25 C
+25 C
?40 C
?40 C
0.8
+85 C
+85 C
0.2
0.6
0.4
0.0
0.2
?0.2
0.0
?0.2
?0.4
?0.4
?0.6
?0.6
?0.8
?0.8
?1.0
0
200
400
600
1000
800
800
0
200
400
600
1000
DIGITAL CODE
DIGITAL CODE
TPC 1. INL vs. Code, TA =  40 C,
25 C,
40 C,
25 C,
TPC 4. R-DNL vs. Code, TA =
85 C Overlay, RAB = 25 k
85 C Overlay, RAB = 25 k
1.0
70
+25 C
?40 C
VDD/VSS = 5V/0V
0.8
60
+85 C
TA = 25 C
0.6
50
0.4
25k
VERSION
40
0.2
250k
VERSION
30
0.0
?0.2
20
?0.4
10
?0.6
0
?0.8
?10
?1.0
?20
?1.2
?1.4
?30
800
0
200
400
600
1000
256
384
512
640
768
896
1023
0
128
DIGITAL CODE
CODE ? Decimal
TPC 2. DNL vs. Code, TA =  40 C,
25 C,
TPC 5. VWB /T Potentiometer Mode Tempco
85 C Overlay, RAB = 25 k
1.0
120
+25 C
VDD/VSS = 5V/0V
?40 C
100
TA = 25 C
+85 C
0.8
80
0.6
60
0.4
40
0.2
20
0
0.0
?20
?0.2
25k
VERSION
?40
250k
VERSION
?0.4
?60
?0.6
?80
800
0
200
400
600
1000
0
128
256
384
512
640
768
896
1023
DIGITAL CODE
CODE ? Decimal
TPC 3. RINL vs. Code, TA =  40 C,
25 C,
TPC 6. RWB /T Rheostat Mode Tempco
85 C Overlay, RAB = 25 k
REV. A
?7?
AD5235
0.28
36
VDD = 3V
DD/VSS =  2.5V
34
VSS = 0V
VA = 1V RMS
0.24
TA = 25 C
32
0.20
30
V
AB = 250k
28
0.16
26
0.12
24
R
25k
22
0.08
20
0.04
18
0.00
16
0
200
1.2k
400
600
800
1.0k
0.01k
0.1k
1k
10k
100k
CODES
FREQUENCY ? Hz
TPC 7. Wiper ON Resistance vs. Code
TPC 10. Total Harmonic Distortion vs. Frequency
4
3
3
0
T
RAB =25k
IDD @ V DD/VSS = 5V/0V
2
?3
RAB = 250k
f?3dB = 12kHz
1
?6
ISS @ V DD/VSS = 5V/0V
f?3dB = 125kHz
0
?9
VDD/VSS =  2.5V
IDD @ V DD/VSS = 2.7V/0V
VA = 1V RMS
ISS @ V DD/VSS = 2.7V/0V
D = MIDSCALE
?1
?12
40
60
80
?40
?20
0
20
100
1k
10k
100k
1M
TEMPERATURE ? C
FREQUENCY ? Hz
TPC 8. IDD vs. Temperature, RAB = 25 k
PC 11. ?3 dB Bandwidth vs. Resistance
(Test Circuit 7)
0
0.25
VDD/VSS = 5V/0V
CODE 200H
T
RAR = 25k
FULL SCALE
?10
100H
0.20
080H
MIDSCALE
?20
040H
0.15
ZERO SCALE
020H
?30
010H
0.10
008H
?40
004H
002H
0.05
?50
001H
?60
0.00
10k
100k
1M
1k
0.0E+00
2.0E+06
4.0E+06
6.0E+06
8.0E+06
1.0E+07
1.2E+07
FREQUENCY ? Hz
FREQUENCY ? Hz
PC 9. IDD vs. Clock Frequency, RAB = 25 k
TPC 12. Gain vs. Frequency vs. Code, RAB = 25 k
(Test Circuit 7)
?8?
REV. A
AD5235
0
2.64
CODE 200H
VDD = VSS = 5V/0V
2.62
CODE = 200H TO 1FFH
?10
100H
2.60
080H
2.58
?20
2.56
040H
020H
2.54
?30
010H
2.52
2.50
008H
?40
2.48
004H
2.46
?50
002H
2.44
001H
?60
2.42
10k
100k
1M
1k
0
10
20
30
40
50
TIME ? s
FREQUENCY ? Hz
TPC 13. Gain vs. Frequency vs. Code, RAB = 250 k
TPC 16. Midscale Glitch Energy, RAB = 25 k,
(Test Circuit 7)
Code 200H to 1 FFH
2.65
80
70
2.60
60
R
RAB = 25k
50
2.55
T
AB = 250k
40
2.50
30
20
VDD = 5V  100mV AC
2.45
VSS = 0V, VA = 5V, VB = 0V
10
MEASURED AT VW WITH CODE = 200 H
TA = 25 C
0
2.40
0
10
20
30
40
50
0.1k
10k
1M
1k
100k
10M
0.01k
TIME ? s
FREQUENCY ? Hz
TPC 17. Midscale Glitch Energy, RAB = 250 k,
PC 14. PSRR vs. Frequency
Code 200H to 1 FFH
VA = V DD
CS
VB = 0
5V/DIV
VDD
TA = 25 C
0.5V/DIV
0.5V/DIV
VW(D)
CLK
5V/DIV
0.5V/DIV
SDI
5V/DIV
MIDSCALE
IDD
20mA/DIV
50 S/DIV
4ms/DIV
TPC 15. Power-On Reset, VDD = 2.25 V, Previously
TPC 18. IDD vs. Time (Save) Program Mode
Stored Code, D = 2AA H
REV. A
?9?
AD5235
100
VA = VB = OPEN
TA = 25 C
5V/DIV
CS
10
5V/DIV
CLK
1
RAB = 2Rk
5
5V/DIV
SDI
IDD
0.1
2mA/DIV
8
= 250k
AB
4ms/DIV
*SUPPLY CURRENT RETURNS TO MINIMUM POWER
CONSUMPTION IF INSTRUCTION #0 (NOP) IS EXECUTED
0.01
IMMEDIATELY AFTER INSTRUCTION #1 (READ EEMEM)
0
128
256
384
512
640
768
96
1024
CODE ? Decimal
TPC 19. IDD vs. Time (Read) Program Mode*
TPC 20. IWB_MAX vs. Code
TEST CIRCUITS
Test Circuits 1 to 10 define the test conditions used in the product
specification table.
NC
DUT
VA
IW
A
V+ = V DD
10%
W
VMS
)
(
PSRR (dB) = 20 LOG
VDD
A
VDD
W
B
~
V+
VMS%
VMS
B
PSS (%/%) =
VMS
VDD%
NC = NO CONNECT
Test Circuit 1. Resistor Position Nonlinearity
Test Circuit 4. Power Supply Sensitivity (PSS, PSRR)
Error (Rheostat Operation; R-INL, R-DNL)
A
DUT B
5V
V+ = V DD
DUT
W
1LSB = V+/2N
VIN
A
W
VOUT
OP279
V+
OFFSET
B
GND
VMS
OFFSET BIAS
Test Circuit 5. Inverting Gain
Test Circuit 2. Potentiometer Divider
Nonlinearity Error (INL, DNL)
5V
DUT
OP279
VOUT
IW = V DD/RNOMINAL
VIN
A
VW
W
W
VMS2
OFFSET
B
GND
A
DUT
B
RW = [VMS1 ? V MS2]/ IW
VMS1
OFFSET BIAS
Test Circuit 3. Wiper Resistance
Test Circuit 6. Noninverting Gain
?10?
REV. A
AD5235
TEST CIRCUITS (continued)
NC
+15V
A
VDD
ICM
A
DUT
W
W
VIN
DUT
OP42
VOUT
VSS GND
B
B
OFFSET
VCM
GND
2.5V
?15V
NC
NC = NO CONNECT
Test Circuit 7. Gain vs. Frequency
Test Circuit 9. Common-Mode Leakage Current
0.1V
VDD
RSW =
A1
A2
ISW
DUT
RDAC1
RDAC2
CODE = 000H
VIN
W
W2
W1
+
VOUT
NC
B
0.1V
ISW
B2
VSS
B1
VSS TO VDD
CTA = 20 LOG [VOUT/VIN]
NC = NO CONNECT
Test Circuit 8. Incremental ON Resistance
Test Circuit 10. Analog Crosstalk
7. Decrement All One Step
OPERATIONAL OVERVIEW
The AD5235 digital potentiometer is designed to operate as a
8. Reset EEMEM Setting to RDAC
true variable resistor. The resistor wiper position is determined by
9. Read EEMEM to SDO
the RDAC register contents. The RDAC register acts as a scratch
10. Read Wiper Setting to SDO
pad register that allows unlimited changes of resistance settings.
11. Write Data to RDAC
The scratch pad register can be programmed with any position
12. Increment 6 dB
setting using the standard SPI serial interface by loading the 24-bit
13. Increment All 6 dB
data-word. The format of the data-word is that the first 4 bits are
14. Increment One Step
commands, the following 4 bits are addresses, and the last 16 bits
15. Increment All One Step
are data. Once a specific value is set, this value can be saved into
a corresponding EEMEM register. During subsequent power-up,
Tables X to XVI provide programming examples by using some
the wiper setting will automatically be loaded at that value. Saving
of these commands.
data to the EEMEM takes about 25 ms and consumes approximately
Scratch Pad and EEMEM Programming
20 mA. During this time, the shift register is locked, preventing any
The basic mode of setting the digital potentiometer wiper position
changes from taking place. The RDY pin indicates the completion
(programming the scratch pad register) is accomplished by loading
of this EEMEM saving process. There are also 13 addresses, with
the serial data input register with the command 11, the corre-
2 bytes each, of user-defined data that can be stored in EEMEM.
sponding address, and the data. Since the scratch pad register is a
OPERATION DETAIL
standard logic register, there is no restriction on the number of
There are 16 commands that facilitate users' programming needs.
changes allowed. When the desired wiper position is determined, the
Refer to Table II. The commands are:
user can load the serial data input register with the command 2,
which stores the setting into the corresponding EEMEM register.
0.
Do Nothing
The EEMEM value can be changed at any time or permanently
1.
Restore EEMEM Setting to RDAC
protected by activating the WP command. Table III provides a
2.
Save RDAC Setting to EEMEM
programming example listing the sequence of serial data input
3.
Save User Data or RDAC Setting to EEMEM
(SDI) words and the corresponding serial data output (SDO) in
4.
Decrement 6 dB
hexadecimal format.
5.
Decrement All 6 dB
6.
Decrement One Step
REV. A
?11?
AD5235
Table I. 24-Bit Serial Data-Word
MSB
Command Byte 0
Data Byte 1
Data Byte 0
LSB
RDAC
C3 C2 C1 C0 0
0
0
A0 X
X
X
X
X
X
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EEMEM C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Command bits are C0 to C3. Address bits are A3 to A0. Data bits D0 to D9 are applicable to RDAC wiper register whereas D0 to D15 are applicable to EEMEM
register. Command codes are defined in Table II.
Table II. Command Operation Truth Table1, 2, 3
Command Command Byte 0
Data Byte 1
Data Byte 0  Operation
Number  B23 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? B16 B15 ? ? ? ? ? ? B8 B7 ? ? ? ? ? B0
C3 C2 C1 C0 A3 A2 A1 A0
X ? ? ? ? D9 D8
D7 ? ? ? ? ? D0
0
0
0
0
0
XXX
X
X????X
X
X ? ? ? ? ? ? X NOP: Do nothing. See Table XII.
1
0
0
0
1
0
0
0
A0
X????X
X
X ? ? ? ? ? ? X Write contents of EEMEM(A0) to RDAC(A0) Register.
This command leaves device in the read program
power state. To return part to the idle state, perform
NOP command 0. See Table XII.
2
0
0
1
0
0
0
0
A0
X????X
X
X??????X
Save Wiper Setting: Write contents of RDAC(A0) to
EEMEM(A0). See Table XI.
34
0
0
1
1
A3 A2 A1 A0
D15 ? ? ? ? D8
D7 ? ? ? ? ? D0 Write contents of Serial Register Data Bytes 0 and 1
(total 16-bit) to EEMEM(ADDR). See Table XIV.
45
0
1
0
0
0
0
0
A0
X????X
X
X??????X
Decrement 6 dB: Right shift contents of RDAC(A0),
register, stops at all "zeros."
55
0
1
0
1
XXX
X
X????X
X
X??????X
Decrement all 6 dB: Right shift contents of all RDAC
registers, stops at all "zeros."
65
0
1
1
0
0
0
0
A0
X????X
X
X??????X
Decrement contents of RDAC(A0) by "one," stops
at all "zero."
75
0
1
1
1
XXX
X
X????X
X
X??????X
Decrement contents of all RDAC registers by "one,"
stops at all "zero."
8
1
0
0
0
0
0
0
0
X????X
X
X??????X
RESET: Load all RDACs with their corresponding
EEMEM previously saved values.
9
1
0
0
1
A3 A2 A1 A0
X????X
X
X??????X
Transfer contents of EEMEM(ADDR) to Serial Register
Data Bytes 0 and 1 and previously stored data can be
read out from the SDO pin. See Table XV.
10
1
0
1
0
0
0
0
A0
X????X
X
X??????X
Transfer contents of RDAC(A0) to Serial Register
Data Bytes 0 and 1 and wiper setting can be read out
from SDO pin. See Table XVI.
11
1
0
1
1
0
0
0
A0
X ? ? ? ? D9 D8
D7 ? ? ? ? ? D0 Write contents of Serial Register Data Bytes 0 and 1
(total 10-bit) to RDAC(A0). See Table X.
125
1
1
0
0
0
0
0
A0
X????X
X
X??????X
Increment 6 dB: Left shift contents of RDAC(A0),
stops at all "ones." See Table XIII.
135
1
1
0
1
XXX
X
X????X
X
X??????X
Increment All 6 dB: Left shift contents of all RDAC
registers, stops at all "ones."
145
1
1
1
0
0
0
0
A0
X????X
X
X??????X
Increment contents of RDAC(A0) by "one," stops at
all "ones." See Table XI.
155
1
1
1
1
XXX
X
X????X
X
X??????X
Increment contents of all RDAC registers by "one,"
stops at all "ones."
NOTES
1
The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any command following command 9 or 10, the
selected internal regi