Ij

LC2MOS
16-Bit A/D Converter
AD7701
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Monolithic 16-Bit ADC
AVDD
DVDD  AVSS  DVSS
SC1
SC2
0.0015% Linearity Error
14
15
7
6
4
17
On-Chip Self-Calibration Circuitry
Programmable Low-Pass Filter
AD7701
0.1 Hz to 10 Hz Corner Frequency
0 V to +2.5 V or  2.5 V Analog Input Range
CALIBRATION
CALIBRATION
13 CAL
MICROCONTROLLER
SRAM
4 kSPS Output Data Rate
Flexible Serial Interface
Ultralow Power
16-BIT A/D CONVERTER
AIN
9
12 BP/UP
APPLICATIONS
6-POLE GAUSSIAN
ANALOG
LOW-PASS
Industrial Process Control
MODULATOR
VREF 10
DIGITAL FILTER
11 SLEEP
Weigh Scales
Portable Instrumentation
Remote Data Acquisition
AGND
8
20 SDATA
CLOCK
SERIAL INTERFACE
GENERATOR
LOGIC
19 SCLK
DGND
5
3
2
1
16
18
CLKIN
CLKOUT
CS
DRDY
MODE
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7701 is a 16-bit ADC that uses a sigma-delta conversion
1. The AD7701 offers 16-bit resolution coupled with outstand-
technique. The analog input is continuously sampled by an analog
ing 0.0015% accuracy.
modulator whose mean output duty cycle is proportional to the
2. No missing codes ensures true, usable, 16-bit dynamic range,
input signal. The modulator output is processed by an on-chip
removing the need for programmable gain and level-setting
digital filter with a six-pole Gaussian response, which updates
circuitry.
the output data register with 16-bit binary words at word rates up
3. The effects of temperature drift are eliminated by on-chip
to 4 kHz. The sampling rate, filter corner frequency, and output
self-calibration, which removes zero and gain error. External
word rate are set by a master clock input that may be supplied
circuits can also be included in the calibration loop to remove
externally, or by a crystal controlled on-chip clock oscillator.
system offsets and gain errors.
4. A flexible synchronous/asynchronous interface allows the
The inherent linearity of the ADC is excellent and endpoint
AD7701 to interface directly to UARTs or to the serial ports
accuracy is ensured by self-calibration of zero and full scale,
of industry-standard microcontrollers.
which may be initiated at any time. The self-calibration scheme
5. Low operating power consumption and an ultralow power
can also be extended to null system offset and gain errors in the
standby mode make the AD7701 ideal for loop-powered
input channel.
remote sensing applications, or battery-powered portable
The output data is accessed through a flexible serial port, which
instruments.
has an asynchronous mode compatible with UARTs and two
synchronous modes suitable for interfacing to shift registers or
the serial ports of industry-standard microcontrollers.
CMOS construction ensures low power dissipation, and a power-
down mode reduces the idle power consumption to only 10 ?W.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise
Tel: 781/329-4700
www.analog.com
under any patent or patent rights of Analog Devices. Trademarks and
Fax: 781/326-8703
? 2003 Analog Devices, Inc. All rights reserved.
registered trademarks are the property of their respective companies.
ApDa7Mode:1?SPECISource ATION=S1k (T1 with 1CnFAVto AGND at = +5unless otherwise=noted.)V
70  MODE = +5 V; A FICResistance      = 25 ;    = DV  A ; V; AV = DV   ?5 V;
= +2.5 V; fCLKIN = 4.096 MHz;
A
DD
DD
SS
SS
REF
Bi ol r
IN
IN
A, S Version2
B, T Version2
Parameter
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
16
16
Bits
Integral Nonlinearity
? 0.0007
TMIN to TMAX
% FSR typ
? 0.003
? 0.0015
% FSR max
Differential Nonlinearity
? 0.125
? 0.125
TMIN to TMAX
LSB typ
Guaranteed No Missing Codes
? 0.5
? 0.5
LSB max
? 0.13
? 0.13
Positive Full-Scale Error3
LSB typ
? 0.5
? 0.5
LSB max
? 1.2 (? 2.3 S Version)
? 1.2 (? 2.3 T Version)
Full-Scale Drift4
LSB typ
? 0.25
? 0.25
Unipolar Offset Error3
LSB typ
?1
?1
LSB max
? 1.6 (+3/?25 S Version)
? 1.6 (+3/?25 T Version)
Unipolar Offset Drift4
LSB typ
? 0.25
? 0.25
Bipolar Zero Error3
LSB typ
?1
?1
LSB max
? 0.8 (+1.5/?12.5 S Version)
? 0.8 (+1.5/?12.5 T Version)
Bipolar Zero Drift4
LSB typ
? 0.5
? 0.5
Bipolar Negative Full-Scale Error3
LSB typ
?2
?2
LSB max
? 0.6 (? 1.2 S Version)
? 0.6 (? 1.2 T Version)
Bipolar Negative Full-Scale Drift4
LSB typ
Noise (Referred to Output)
0.1
0.1
LSB rms typ
DYNAMIC PERFORMANCE
Sampling Frequency, fS
fCLKIN/256
fCLKIN/256
Hz
Output Update Rate, fOUT
fCLKIN/1024
fCLKIN/1024
Hz
Filter Corner Frequency, f?3 dB
fCLKIN/409,600
fCLKIN/409,600
Hz
Settling Time to ? 0.0007% FS
507904/fCLKIN
507904/fCLKIN
sec
For Full-Scale Input Step
SYSTEM CALIBRATION
Applies to unipolar and
Positive Full-Scale Overrange
VREF + 0.1
VREF + 0.1
V max
bipolar ranges. After cali-
Positive Full-Scale Overrange
VREF + 0.1
VREF + 0.1
V max
bration, if AIN > VREF, the
Negative Full-Scale Overrange
?(VREF + 0.1)
?(VREF + 0.1)
V max
device will output all 1s.
Maximum Offset Calibration Range5, 6
If AIN < 0 (unipolar) or
Unipolar Input Range
?(VREF + 0.1)
?(VREF + 0.1)
V max
?VREF (bipolar), the device
Bipolar Input Range
?0.4 VREF to +0.4 VREF
?0.4 VREF to +0.4 VREF
V max
will output all 0s.
Input Span7
0.8 VREF
0.8 VREF
V min
2 VREF + 0.2
2 VREF + 0.2
V max
ANALOG INPUT
Unipolar Input Range
0 to 2.5
0 to 2.5
V
? 2.5
? 2.5
Bipolar Input Range
V
Input Capacitance
10
10
pF typ
Input Bias Current1
1
1
nA typ
LOGIC INPUTS
All Inputs Except CLKIN
VINL, Input Low Voltage
0.8
0.8
V max
VINH, Input High Voltage
2.0
2.0
V min
CLKIN
VINL, Input Low Voltage
0.8
0.8
V max
VINH, Input High Voltage
3.5
3.5
V min
?A max
IIN, Input Current
10
10
LOGIC OUTPUTS
VOL, Output Low Voltage
0.4
0.4
V max
ISINK = 1.6 mA
ISOURCE = 100 ?A
VOH, Output High Voltage
DVDD ? 1
DVDD ? 1
V min
? 10
? 10
?A max
Floating State Leakage Current
Floating State Output Capacitance
9
9
pF typ
?2?
REV. E
AD7701
A, S Version2
B, T Version2
Parameter
Unit
Test Conditions/Comments
POWER REQUIREMENTS8
Power Supply Voltages
Analog Positive Supply (AVDD)
4.5/5.5
4.5/5.5
V min/V max
Digital Positive Supply (DVDD)
4.5/AVDD
4.5/AVDD
V min/V max
Analog Negative Supply (AVSS)
?4.5/?5.5
?4.5/?5.5
V min/V max
Digital Negative Supply (DVSS)
?4.5/?5.5
?4.5/?5.5
V min/V max
Calibration Memory Retention
Power Supply Voltage
2.0
2.0
V min
DC Power Supply Currents8
Analog Positive Supply (AIDD)
2.7
2.7
mA max
Typically 2 mA
Digital Positive Supply (DIDD)
2
2
mA max
Typically 1 mA
Analog Negative Supply (AISS)
2.7
2.7
mA max
Typically 2 mA
Digital Negative Supply (DISS)
0.1
0.1
mA max
Typically 0.03 mA
Power Supply Rejection9
Positive Supplies
70
70
dB typ
Negative Supplies
75
75
dB typ
Power Dissipation
SLEEP = Logic 1,
Normal Operation
37
37
mW max
Typically 25 mW
?W max
SLEEP = Logic 0,
Standby Operation10
20 (40 S Version)
20 (40 T Version)
Typically 10 ?W
NOTES
1
The AIN pin presents a very high impedance dynamic load that varies with clock frequency.
Temperature ranges are as follows: A, B Versions: ?40 ?C to +85?C; S, T Versions: ?55?C to +125?C.
2
3
Apply after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges.
Total drift over the specified temperature range since calibration at power-up at 25 ?C. This is guaranteed by design and/or characterization. Recalibration at
4
any temperature will remove these errors.
5
In Unipolar mode, the offset can have a negative value (?V  REF) such that the Unipolar mode can mimic Bipolar mode operation.
6
The specifications for input overrange and for input span apply additional constraints on the offset calibration range.
7
For Unipolar mode, input span is the difference between full scale and zero scale. For Bipolar mode, input span is the difference between positive and
negative full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ? (VREF +0.1).
8
All digital outputs unloaded. All digital inputs at 5 V CMOS levels.
9
Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.
10
CLKIN is stopped. All digital inputs are grounded.
Specifications subject to change without notice.
REV. E
?3?
AD7701
ABSOLUTE MAXIMUM RATINGS1
Operating Temperature Range
Commercial Plastic (A, B Versions) . . . . . ?40?C to +85?C
(TA = 25?C, unless otherwise noted.)
Industrial CERDIP (A, B Versions) . . . . . . ?40?C to +85?C
DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . ?0.3 V to +6 V
Extended CERDIP (S, T Versions) . . . . . ?55?C to +125?C
DVDD to AVDD  . . . . . . . . . . . . . . . . . . . . . . . ?0.3 V to +0.3 V
Storage Temperature Range. . . . . . . . . . . . . ?65?C to +150?C
DVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to ?6 V
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300?C
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . ?0.3 V to +6 V
Power Dissipation (Any Package) to 75?C . . . . . . . . . 450 mW
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to ?6 V
Derates above 75?C by . . . . . . . . . . . . . . . . . . . . . 10 mW/?C
AGND to DGND . . . . . . . . . . . . . . . . . . . . . ?0.3 V to +0.3 V
NOTES
Digital Input Voltage to DGND . . . . ?0.3 V to DVDD + 0.3 V
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
Analog Input
nent damage to the device. This is a stress rating only; functional operation of the
Voltage to AGND . . . . . . . . AVSS ? 0.3 V to AVDD + 0.3 V
device at these or any other conditions above those listed in the operational
Input Current to Any Pin Except Supplies2 . . . . . . . . ? 10 mA
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Temperature
Linearity
Package
Options*
Model
Range
Error (% FSR)
?40?C to +85?C
AD7701AN
0.003
N-20
?40?C to +85?C
AD7701BN
0.0015
N-20
?40?C to +85?C
AD7701AR
0.003
R-20
?40?C to +85?C
AD7701BR
0.0015
R-20
?40?C to +85?C
AD7701ARS
0.003
RS-28
?40?C to +85?C
AD7701AQ
0.003
Q-20
?40?C to +85?C
AD7701BQ
0.0015
Q-20
?55?C to +125?C
AD7701SQ
0.003
Q-20
?55?C to +125?C
AD7701TQ
0.0015
Q-20
*N = PDIP; Q = CERDIP; R = SOIC; RS = SSOP.
PIN CONFIGURATIONS
PDIP, CERDIP, SOIC
SSOP
MODE 1
20 SDATA
MODE 1
28 SDATA
19 SCLK
27 SCLK
CLKOUT 2
CLKOUT 2
18 DRDY
CLKIN 3
26 DRDY
CLKIN 3
17 SC2
25 SC2
SC1 4
SC1 4
AD7701
16 CS
24 CS
DGND 5
DGND 5
TOP VIEW
DVSS  6 (Not to Scale) 15 DVDD
23 NC
NC 6
AD7701
14 AVDD
AVSS  7
22 NC
NC 7
TOP VIEW
13 CAL
DVSS 8
(Not to Scale) 21 NC
AGND 8
12 BP/UP
20 DVDD
AIN  9
NC 9
VREF 10
AVSS 10
19 AVDD
11 SLEEP
NC 11
18 NC
17 CAL
AGND 12
AIN 13
16 BP/UP
VREF 14
15 SLEEP
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7701 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
?4?
REV. E
AD7701
PIN FUNCTION DESCRIPTIONS
Pin No.
PDIP,
CERDIP,
SOIC
SSOP
Mnemonic Description
1
1
MODE
Selects the Serial Interface Mode. If MODE is tied to ?5 V, the AD7701 will operate in
the Asynchronous Communications (AC) mode. The SCLK pin is configured as an
input, and data is transmitted in two bytes, each with one start bit and two stop bits. If
MODE is tied to DGND, the Synchronous External Clocking (SEC) mode is selected.
SCLK is configured as an input, and the output appears without formatting, the MSB
coming first. If MODE is tied to +5 V, the AD7701 operates in the Synchronous
Self-Clocking (SSC) mode. SCLK is configured as an output, with a clock frequency of
fCLKlN/4 and 25% duty cycle.
2
2
CLKOUT
Clock Output to Generate an Internal Master Clock by Connecting a Crystal between
CLKOUT and CLKIN. If an external clock is used, CLKOUT is not connected.
3
3
CLKIN
Clock Input for External Clock.
4, 17
4, 25
SC1, SC2
System Calibration Pins. The state of these pins, when CAL is taken high, determines
the type of calibration performed.
5
5
DGND
Digital Ground. Ground reference for all digital signals.
6
8
DVSS
Digital Negative Supply, ?5 V Nominal.
6, 7, 9, 11,
NC
No Connect.
18, 21, 22, 23
7
10
AVSS
Analog Negative Supply, ?5 V Nominal.
8
12
AGND
Analog Ground. Ground reference for all analog signals.
9
13
AIN
Analog Input.
10
14
VREF
Voltage Reference Input, 2.5 V Nominal. This determines the value of positive full scale
in the Unipolar mode and of both positive and negative full scale in Bipolar mode.
SLEEP
11
15
Sleep Mode Pin. When this pin is taken low, the AD7701 goes into a low power mode
with typically 10 ?W power consumption.
BP/UP
12
16
Bipolar/Unipolar Mode Pin. When this pin is low, the AD7701 is configured for a uni-
polar input range going from AGND to VREF. When Pin 12 is high, the AD7701 is
configured for a bipolar input range, ? VREF.
13
17
CAL
Calibration Mode Pin. When CAL is taken high for more than four cycles, the AD7701
is reset and performs a calibration cycle when CAL is brought low again. The CAL pin
can also be used as a strobe to synchronize the operation of several AD7701s.
14
19
AVDD
Analog Positive Supply, +5 V Nominal.
15
20
DVDD
Digital Positive Supply, +5 V Nominal.
CS
Chip Select Input. When CS is brought low, the AD7701 will begin to transmit serial
16
24
data in a format determined by the state of the MODE pin.
DRDY
Data Ready Output. DRDY is low when valid data is available in the output register. It
18
26
goes high after transmission of a word is completed. It also goes high for four clock
cycles when a new data-word is being loaded into the output register, to indicate that
valid data is not available, irrespective of whether data transmission is complete or not.
19
27
SCLK
Serial Clock Input/Output. The SCLK pin is configured as an input or output, depen-
dent on the type of serial data transmission that has been selected by the MODE pin.
When configured as an output in the Synchronous Self-Clocking mode, it has a fre-
quency of fCLKIN/4 and a duty cycle of 25%.
20
28
SDATA
Serial Data Output. The AD7701's output data is available at this pin as a 16-bit serial
word. The transmission format is determined by the state of the MODE pin.
REV. E
?5?
AD7701
(AVDD = DVDD = +5 V  10%; AVSS = DVSS = ?5 V  10%; AGND = DGND = O V; fCLKIN =
TIMING CHARACTERISTICS1, 2
4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DVDD; unless otherwise noted.)
Limit at TMIN, TMAX  Limit at TMIN, TMAX
Parameter
(A, B Versions)
(S, T Versions)
Unit
Conditions/Comments
fCLKIN3, 4
200
200
kHz min
Master Clock Frequency: Internal Gate Oscillator.
5
5
MHz max
Typically 4.096 MHz.
200
200
kHz min
Master Clock Frequency: Externally Supplied.
5
5
MHz max
tr5
50
50
ns max
Digital Output Rise Time. Typically 20 ns.
tf5
50
50
ns max
Digital Output Fall Time. Typically 20 ns.
t1
0
0
ns min
SC1, SC2 to CAL High Setup Time.
50
50
ns min
SC1, SC2 Hold Time after CAL Goes High.
t2
SLEEP High to CLKIN High Setup Time.
t36
1000
1000
ns min
SSC MODE
Data Access Time (CS Low to Data Valid).
t47
3/fCLKIN
3/fCLKIN
ns max
t5
100
100
ns max
SCLK Falling Edge to Data Valid Delay (25 ns typ).
250
250
ns min
MSB Data Setup Time. Typically 380 ns.
t6
300
300
ns max
SCLK High Pulsewidth. Typically 240 ns.
t7
t8
790
790
ns max
SCLK Low Pulsewidth. Typically 730 ns.
t98
l/fCLKIN +200
l/fCLKIN +200
ns max
SCLK Rising Edge to Hi-Z Delay (l/fCLKIN + 100 ns typ).
CS High to Hi-Z Delay.
t108, 9
(4/fCLKIN) +200
(4/fCLKIN) +200
ns max
SEC MODE
fSCLK
5
5
MHz
Serial Clock Input Frequency.
t11
35
35
ns min
SCLK Input High Pulsewidth.
160
160
ns min
SCLK Low Pulsewidth.
t12
Data Access Time (CS Low to Data Valid). Typically 80 ns.
t137, 10
160
160
ns max
t1411
150
150
ns max
SCLK Falling Edge to Data Valid Delay. Typically 75 ns.
CS High to Hi-Z Delay.
t158
250
250
ns max
t168
200
200
ns max
SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
AC MODE
CS Setup Time. Typically 20 ns.
t17
40
40
ns min
180
180
ns max
Data Delay Time. Typically 90 ns.
t18
t19
200
200
ns max
SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
NOTES
Sample tested at 25?C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
1
2
See Figures 1 to 6.
3
CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7701 is not in SLEEP mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.
4
The AD7701 is production tested with fCLKIN at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
5
Specified using 10% and 90% points on waveform of interest.
In order to synchronize several AD7701s together using the SLEEP pin, this specification must be met.
6
7
t4 and t13 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
8
t9, t10, t15, and t16 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is
the true bus relinquish time of the part and as such is independent of external bus loading capacitance.
If CS is returned high before all 16 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.
9
If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be
10
as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high
sooner than four CLKIN cycles plus 160 ns after CS goes low.
11
SDATA is clocked out on the falling edge of the SCLK input.
Specifications subject to change without notice.
?6?
REV. E
AD7701
IOL
1.6mA
CAL
TO
CLKIN
+2.1V
OUTPUT
CL
PIN
t2
t1
t3
100pF
IOH
SC1, SC2
SC1, SC2 VALID
SLEEP
200?A
Figure 2b. SLEEP Mode Timing
Figure 2a. Calibration Control Timing
Figure 1. Load Circuit for Access
Time and Bus Relinquish Time
DRDY
CS
t12
t11
CS
SCLK
CS
t15
t13
t16
t14
t10
HI-Z
DATA
HI-Z
SDATA
HI-Z
VALID
HI-Z
SDATA
DB15 DB14
DB0
DB1
DATA
SDATA
VALID
Figure 4a. SEC Mode Data Hold Time
Figure 3. SSC Mode Data
Figure 4b. SEC Mode Timing Diagram
Hold Time
CLKIN
CS
DRDY
t7
CS
t8
HI-Z
t17
SCLK
SCLK
t4
t5
t18
t19
t6
START
t5
HI-Z
HI-Z
SDATA
HI-Z
HI-Z
STOP 1
DB8
DB7
DB9
STOP 2
SDATA
DB15
DB14
DB1
DB0
LOW BYTE
HIGH BYTE
Figure 5. SSC Mode Timing Diagram
Figure 6. AC Mode Timing Diagram
DEFINITION OF TERMS
Bipolar Zero Error
Linearity Error
This is the deviation of the midscale transition (0111 . . . 111 to
This is the maximum deviation of any code from a straight line
1000 . . . 000) from the ideal (AGND ? 0.5 LSB) when operating
passing through the endpoints of the transfer function. The
in the Bipolar mode. It is expressed in microvolts.
endpoints of the transfer function are zero scale (not to be
Bipolar Negative Full-Scale Error
confused with bipolar zero), a point 0.5 LSB below the first
This is the deviation of the first code transition from the ideal
code transition (000 . . . 000 to 000 . . . 001) and full scale, a
(?VREF + 0.5 LSB) when operating in the Bipolar mode. It is
point 1.5 LSB above the last code transition (111 . . . 110 to
expressed in microvolts.
111 . . . 111). The error is expressed as a percentage of full scale.
Positive Full-Scale Overrange
Differential Linearity Error
Positive full-scale overrange is the amount of overhead available
This is the difference between any code's actual width and the
to handle input voltages greater than +VREF (for example, noise
ideal (1 LSB) width. Differential linearity error is expressed in
peaks or excess voltages due to system gain errors in system
LSBs. A differential linearity specification of ? 1 LSB or less
calibration routines) without introducing errors due to overloading
guarantees monotonicity.
the analog modulator or overflowing the digital filter. It is
Positive Full-Scale Error
expressed in millivolts.
Positive full-scale error is the deviation of the last code transition
Negative Full-Scale Overrange
(111 . . . 110 to 111 . . . 111) from the ideal (VREF ? 3/2 LSBs).
This is the amount of overhead available to handle voltages below
It applies to both positive and negative analog input ranges and
?VREF without overloading the analog modulator or overflowing
is expressed in microvolts.
the digital filter. Note that the analog input will accept negative
Unipolar Offset Error
voltage peaks even in the Unipolar mode. The overhead is
Unipolar offset error is the deviation of the first code transition
expressed in millivolts.
from the ideal (AGND + 0.5 LSB) when operating in the Uni-
polar mode. It is expressed in microvolts.
REV. E
?7?
AD7701
The AD7701 can perform self-calibration using the on-chip
Offset Calibration Range
calibration microcontroller and SRAM to store calibration
In the system calibration modes (SC2 low), the AD7701 cali-
parameters. A calibration cycle may be initiated at any time
brates its offset with respect to the AIN pin. The offset calibration
using the CAL control input.
range specification defines the range of voltages, expressed as a
percentage of VREF, that the AD7701 can accept and still accu-
Other system components may also be included in the calibra-
rately calibrate offset.
tion loop to remove offset and gain errors in the input channel.
Full-Scale Calibration Range
For battery operation, the AD7701 also offers a standby mode
This is the range of voltages that the AD7701 can accept in the
that reduces idle power consumption to typically 10 ?W.
system calibration mode and still correctly calibrate full scale.
THEORY OF OPERATION
Input Span
The general block diagram of a sigma-delta ADC is shown in
In system calibration schemes, two voltages applied in sequence
Figure 8. It contains the following elements:
to the AD7701's analog input define the analog input range.
The input span specification defines the minimum and maxi-
1.
A sample-hold amplifier
mum input voltages from zero to full scale that the AD7701 can
2.
A differential amplifier or subtracter
accept and still accurately calibrate gain. The input span is
3.
An analog low-pass filter
expressed as a percentage of VREF.
4.
A 1-bit A/D converter (comparator)
5.
A 1-bit DAC
GENERAL DESCRIPTION
6.
A digital low-pass filter
The AD7701 is a 16-bit A/D converter with on-chip digital
In operation, the analog signal sample is fed to the subtracter,
filtering, intended for the measurement of wide dynamic range,
along with the output of the 1-bit DAC. The filtered difference
low frequency signals such as those representing chemical,
signal is fed to the comparator, whose output samples the differ-
physical, or biological processes. It contains a charge-balancing
ence signal at a frequency many times that of the analog signal
(sigma-delta) ADC, calibration microcontroller with on-chip
sampling frequency (oversampling).
static RAM, clock oscillator, and serial communications port.
The analog input signal to the AD7701 is continuously sampled
S/H AMP
at a rate determined by the frequency of the master clock, CLKIN.
COMPARATOR
ANALOG
A charge-balancing A/D converter (sigma-delta modulator)
LOW-PASS
DIGITAL
FILTER
converts the sampled signal into a digital pulse train whose duty
FILTER
cycle contains the digital information. A six-pole Gaussian digi-
tal low-pass filter processes the output of the modulator and
DIGITAL DATA
DAC
updates the 16-bit output register at a 4 kHz rate. The output
data can be read from the serial port randomly or periodically at
any rate up to 4 kHz.
Figure 8. General Sigma-Delta ADC
Oversampling is fundamental to the operation of sigma-delta
+5V
ANALOG
ADCs. Using the quantization noise formula for an ADC:
SUPPLY
0.1?F
10?F
SNR = (6.02 ?number of bits + 1.76) dB
DVDD
AVDD
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
0.1?F
SLEEP
2.5V
VOLTAGE
The AD7701 samples the input signal at 16 kHz, which spreads
VREF
REFERENCE
MODE
the quantization noise from 0 kHz to 8 kHz. Since the specified
READ
DRDY
analog input bandwidth of the AD7701 is only 0 Hz to 10 Hz,
READY
READ
the noise energy in this bandwidth would be only 1/800 of the
CS
RANGE
(TRANSMIT)
BP/UP
SELECT
total quantization noise, even if the noise energy were spread
SERIAL
SCLK
CLOCK
evenly throughout the spectrum. It is reduced still further by
CALIBRATE
CAL
SERIAL
SDATA
DATA
analog filtering in the modulator loop, which shapes the quanti-
AD7701
zation noise spectrum to move most of the noise energy to
CLKIN
frequencies above 10 Hz. The SNR performance in the 0 Hz to
ANALOG
AIN
INPUT
10 Hz range is conditioned to the 16-bit level in this fashion.
CLKOUT
The output of the comparator provides the digital input for the
SC2
ANALOG
1-bit DAC, so the system functions as a negative feedback loop
AGND
GROUND
DGND
that minimizes the difference signal. The digital data that repre-
0.1?F
0.1?F
DVSS
AVSS
sents the analog input voltage is in the duty cycle of the pulse
train appearing at the output of the comparator. It can be
?5V
ANALOG
retrieved as a parallel binary data-word using a digital filter.
SUPPLY 0.1?F
10?F
Sigma-delta ADCs are generally described by the order of the
analog low-pass filter. A simple example of a first-order, sigma-
delta ADC is shown in Figure 9. This contains only a first-order,
Figure 7. Typical System Connection Diagram
low-pass filter or integrator. It also illustrates the derivation of
the alternative name for these devices: charge-balancing ADCs.
?8?
REV. E
AD7701
Figure 10 shows the filter frequency response. This is a six-pole
C
CLOCK
Gaussian response that provides 55 dB of 60 Hz rejection for a
R
10 Hz cutoff frequency. If the clock frequency is halved to give a
AIN
5 Hz cutoff, 60 Hz rejection is better than 90 dB. A normalized
TO DIGITAL
FILTER
s-domain pole-zero plot of the filter is shown in Figure 11.
INTEGRATOR
The response of the filter is defined by:
STROBED
COMPARATOR
-0.5
R
1 + 0.693x2 + 0.240x4 + 0.0555x6 +
H (x)  = 
+VREF
0.00962x + 0.00133x  + 0.000154x
8
10
12
?VREF
where
1-BIT DAC
x = f f3dB , f3dB = fCLKIN 409600
Figure 9. SEC Basic Charge-Balancing ADC
and f is the frequency of interest.
The term charge-balancing comes from the fact that this system
is a negative feedback loop that tries to keep the net charge on
20
the integrator capacitor at zero by balancing charge injected by
0
the input voltage with charge injected by the 1-bit DAC. When
fCLK = 4MHz
the analog input is zero the only contribution to the integrator
?20
output comes from the 1-bit DAC. For the net charge on the
?40
integrator capacitor to be zero, the DAC output must spend half
its time at +1 V and half its time at ?1 V. Assuming ideal com-
fCLK = 2MHz
?60
ponents, the duty cycle of the comparator will be 50%.
?80
When a positive analog input is applied, the output of the 1-bit
?100
DAC must spend a larger proportion of the time at +1 V, so the
duty cycle of the comparator increases. When a negative input
?120
fCLK = 1MHz
voltage is applied, the duty cycle decreases.
?140
The AD7701 uses a second-order, sigma-delta modulator and a
?160
sophisticated digital filter that provides a rolling average of the
1
100
10
FREQUENCY ? Hz
sampled output. After power-up or if there is a step change in
the input voltage, there is a settling time that must elapse before
Figure 10. Frequency Response of AD7701 Filter
valid data is obtained.
jw
j2
DIGITAL FILTERING
The AD7701's digital filter behaves like an analog filter, with a
few minor differences.
j1
First, since digital filtering occurs after the analog-to-digital
S1,2 = ?1.4663 + j1.8191
s
conversion, it can remove noise injected during the conversion
S3,4 = ?1.7553 + j1.0005
0
process. Analog filtering cannot do this.
?2
?1
S5,6 = ?1.8739 + j0.32272
On the other hand, analog filtering can remove noise super-
?j1
imposed on the analog signal before it reaches the ADC. Digital
filtering cannot do this and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator
?j2
and digital filter, even though the average value of the signal is
within limits. To alleviate this problem, the AD7701 has over-
Figure 11. Normalized Pole-Zero Plot of AD7701 Filter
range headroom built into the sigma-delta modulator and digital
Since the AD7701 contains this on-chip, low-pass filtering,
filter that allows overrange excursions of 100 mV. If noise
there is a settling time associated with step function inputs,
signals are larger than this, consideration should be given to
and data will be invalid after a step change until the settling
analog input filtering, or to reducing the gain in the input
time has elapsed. The AD7701 is, therefore, unsuitable for
channel so that a full-scale input (2.5 V) gives only a half-scale
high speed multiplexing, where channels are switched and
input to the AD7701 (1.25 V). This will provide an overrange
converted sequentially at high rates, as switching between chan-
capability greater than 100% at the expense of reducing the
nels can cause a step change in the input. Rather, it is intended
dynamic range by one bit (50%).
for distributed converter systems using one ADC per channel.
However, slow multiplexing of the AD7701 is possible, pro-
FILTER CHARACTERISTICS
vided that the settling time is allowed to elapse before data for
The cutoff frequency of the digital filter is fCLK/409600. At the
the new channel is accessed.
maximum clock frequency of 4.096 MHz, the cutoff frequency
of the filter is 10 Hz and the output rate is 4 kHz.
REV. E
?9?
AD7701
The output settling of the AD7701 in response to a step input
The input sampling frequency, output data rate, filter character-
change is shown in Figure 12. The Gaussian response has fast
istics, and calibration time are all directly related to the master
settling with no overshoot, and the worst-case settling time to
clock frequency, fCLKIN, by the ratios given in the specification
? 0.0007% (? 0.5 LSB) is 125 ms with a 4.096 MHz master
table. Therefore, the first step in system design with the AD7701 is
clock frequency.
to select a master clock frequency suitable for the bandwidth
and output data rate required by the application.
100
ANALOG INPUT RANGES
The AD7701 performs conversion relative to an externally
80
supplied reference voltage that allows easy interfacing to
ratiometric systems. In addition, either unipolar or bipolar input
60
voltage ranges may be selected using the BP/UP input. With
BP/UP tied low, the input range is unipolar and the span is 0 to
40
+VREF. With BP/UP tied high, the input range is bipolar and the
span is ? VREF. In the Bipolar mode, both positive and negative
20
full scale are directly determined by VREF. This offers superior
tracking of positive and negative full scale and better midscale
0
(bipolar zero) stability than bipolar schemes that simply scale
0
40
80
120
160
TIME ? ms
and offset the input range.
Figure 12. AD7701 Step Response
The digital output coding for the unipolar range is unipolar
binary; for the bipolar range it is offset binary. Bit weights for
USING THE AD7701
the Unipolar and Bipolar modes are shown in Table I. The
SYSTEM DESIGN CONSIDERATIONS
input voltages and output codes for unipolar and bipolar ranges,
The AD7701 operates differently from successive approxima-
using the recommended +2.5 V reference, are shown in
tion ADCs or other integrating ADCs. Since it samples the
Table II.
signal continuously, like a tracking ADC, there is no need for a
start convert command. The 16-bit output register is updated at
Table I. Bit Weight Table (2.5 V Reference Voltage)
a 4 kHz rate, and the output can be read at any time, either
Unipolar Mode
Bipolar Mode
synchronously or asynchronously.
?V
LSBs
% FS
ppm FS
LSBs
% FS
ppm FS
CLOCKING
10
0.26
0.0004
4
0.13
0.0002
2
The AD7701 requires a master clock input, which may be an
19
0.5
0.0008
8
0.26
0.0004
4
external TTL/CMOS compatible clock signal applied to the
38
1.00
0.0015
15
0.5
0.0008
8
CLKIN pin (CLKOUT not used). Alternatively, a crystal of
76
2.00
0.0031
31
1.00
0.0015
15
the correct frequency can be connected between CLKIN and
153
4.00
0.0061
61
2.00
0.0031
31
CLKOUT, when the clock circuit will function as a crystal
controlled oscillator.
Table II. Output Coding
Unipolar Mode
Bipolar Mode
Input Relative to
Input Relative to
FS and AGND
Input (V)
FS and AGND
Input (V)
Output Data
1111 1111 1111 1111
+VREF ? 1.5 LSB
+2.499943
+VREF ? 1.5 LSB
+2.499886
1111 1111 1111 1110
+VREF ? 2.5 LSB
+2.499905
+VREF ? 2.5 LSB
+2.499810
1111 1111 1111 1101
+VREF ? 3.5 LSB
+2.499867
+VREF ? 3.5 LSB
+2.499733
1111 1111 1111 1100
1000 0000 0000 0001
+VREF/2 + 0