Ij

a
2.7 V to 5.5 V, 350 kSPS, 10-Bit
4-/8-Channel Sampling ADCs
AD7811/AD7812
The control registers of the AD7811 and AD7812 allow the
FEATURES
10-Bit ADC with 2.3  s Conversion Time
input channels to be configured as single-ended or pseudo
differential. The control register also features a software convert
The AD7811 has Four Single-Ended Inputs that
start and a software power-down. Two of these devices can
Can Be Configured as Three Pseudo Differential
share the same serial bus and may be individually addressed in
Inputs with Respect to a Common, or as Two Inde-
a multipackage application by hardwiring the device address pin.
pendent Pseudo Differential Channels
The AD7811 is available in a small, 16-lead 0.3" wide, plastic
The AD7812 has Eight Single-Ended Inputs that Can
dual-in-line package (mini-DIP), in a 16-lead 0.15" wide, Small
Be Configured as Seven Pseudo Differential Inputs
Outline IC (SOIC) and in a 16-lead, Thin Shrink Small Out-
with Respect to a Common, or as Four Independent
line Package (TSSOP). The AD7812 is available in a small,
Pseudo Differential Channels
20-lead 0.3" wide, plastic dual-in-line package (mini-DIP), in a
Onboard Track and Hold
20-lead, Small Outline IC (SOIC) and in a 20-lead, Thin Shrink
Onboard Reference 2.5 V  2.5%
Small Outline Package (TSSOP).
Operating Supply Range: 2.7 V to 5.5 V
Specifications at 2.7 V?3.6 V and 5 V  10%
PRODUCT HIGHLIGHTS
DSP-/Microcontroller-Compatible Serial Interface
1. Low Power, Single Supply Operation
High Speed Sampling and Automatic Power-Down Modes
Both the AD7811 and AD7812 operate from a single 2.7 V
Package Address Pin on the AD7811 and AD7812 Allows
to 5.5 V supply and typically consume only 10 mW of power.
Sharing of the Serial Bus in Multipackage Applications
The power dissipation can be significantly reduced at
Input Signal Range: 0 V to VREF
lower throughput rates by using the automatic power-
Reference Input Range: 1.2 V to VDD
down mode e.g., 315 ?W @ 10 kSPS, VDD = 3 V--see
GENERAL DESCRIPTION
Power vs. Throughput.
The AD7811 and AD7812 are high speed, low power, 10-bit
2. 4-/8-Channel, 10-Bit ADC
A/D converters that operate from a single 2.7 V to 5.5 V supply.
The devices contain a 2.3 ?s successive approximation A/D
The AD7811 and AD7812 have four and eight single-ended
input channels respectively. These inputs can be configured
converter, an on-chip track/hold amplifier, a 2.5 V on-chip refer-
as pseudo differential inputs by using the Control Register.
ence and a high speed serial interface that is compatible with the
3. On-chip 2.5 V (? 2.5%) reference circuit that is powered
serial interfaces of most DSPs (Digital Signal Processors) and
microcontrollers. The user also has the option of using an exter-
down when using an external reference.
nal reference by connecting it to the VREF pin and setting the
4. Hardware and Software Control
EXTREF bit in the control register. The VREF pin may be tied
The AD7811 and AD7812 provide for both hardware and
to VDD. At slower throughput rates the power-down mode may
software control of Convert Start and Power-Down.
be used to automatically power down between conversions.
FUNCTIONAL BLOCK DIAGRAMS
VDD
CREF
REFIN
AGND DGND
VDD
CREF
REFIN
AGND
DGND
1.23V
1.23V
AD7812
REF
AD7811
REF
CLOCK
CLOCK
OSC
BUF
OSC
BUF
DOUT
DOUT
VIN1
DIN
DIN
CHARGE
CHARGE
SERIAL
SERIAL
VIN2
RFS
REDISTRIBUTION
REDISTRIBUTION
RFS
PORT
PORT
DAC
VIN3
DAC
TFS
TFS
VIN4
SCLK
VIN1
SCLK
MUX
VIN5
VIN2
MUX
VIN6
VIN3
CONTROL
CONTROL
VIN7
LOGIC
VIN4
LOGIC
VDD/3
VDD/3
COMP
VIN8
COMP
A0 CONVST
A0 CONVST
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
use, nor for any infringements of patents or other rights of third parties
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Fax: 781/326-8703
? Analog Devices, Inc., 2000
(VDD = 2.7 V to 3.6 V, VDD = 5 V  10%, GND = 0 V, VREF = VDD
AD7811/AD7812?SPECIFICATIONS
[EXT]. All specifications ?40 C to +105 C unless otherwise noted.)
Parameter
Y Version
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fIN = 30 kHz Any Channel, fSAMPLE = 350 kHz
Signal to (Noise + Distortion) Ratio1
58
dB min
VREF Internal or External
Total Harmonic Distortion (THD)1
?66
dB max
Peak Harmonic or Spurious Noise1
?80
dB typ
Intermodulation Distortion1, 2
fa = 29 kHz, fb = 30 kHz
Second Order Terms
?67
dB max
Third Order Terms
?67
dB max
Channel-to-Channel Isolation1, 2
?80
dB typ
fIN = 20 kHz
DC ACCURACY
Any Channel
Resolution
10
Bits
Minimum Resolution for Which
No Missing Codes are Guaranteed
10
Bits
?1
Relative Accuracy1
LSB max
?1
Differential Nonlinearity1
LSB max
?2
Gain Error1
LSB max
? 0.75
Gain Error Match1
LSB max
?2
Offset Error1
LSB max
? 0.75
Offset Error Match1
LSB max
ANALOG INPUT
Input Voltage Range
0
V min
VREF
V max
?1
?A max
Input Leakage Current2
Input Capacitance2
20
pF max
REFERENCE INPUTS2
VREF Input Voltage Range
1.2
V min
VDD
V max
?3
?A max
Input Leakage Current
Input Capacitance
20
pF max
ON-CHIP REFERENCE
Nominal 2.5 V
? 2.5
Reference Error
% max
ppm/?C typ
Temperature Coefficient
50
LOGIC INPUTS2
VDD = 5 V ? 10%
VINH, Input High Voltage
2.4
V min
VDD = 5 V ? 10%
VINL, Input Low Voltage
0.8
V max
VDD = 3 V ? 10%
VINH, Input High Voltage
2
V min
VDD = 3 V ? 10%
VINL, Input Low Voltage
0.4
V max
?1
?A max
Input Current, IIN
Typically 10 nA, VIN = 0 V to VDD
Input Capacitance, CIN
8
pF max
LOGIC OUTPUTS
ISOURCE = 200 ?A
Output High Voltage, VOH
VDD = 5 V ? 10%
4
V min
VDD = 3 V ? 10%
2.4
V min
ISINK = 200 ?A
Output Low Voltage, VOL
0.4
V max
?1
?A max
High Impedance Leakage Current
High Impedance Capacitance
15
pF max
CONVERSION RATE
?s max
Conversion time
2.3
Track/Hold Acquisition Time1
200
ns max
REV. B
?2?
AD7811/AD7812
Parameter
Y Version
Unit
Test Conditions/Comments
POWER SUPPLY
VDD
2.7
V min
For Specified Performance
5.5
V max
Digital Inputs = 0 V or VDD
IDD
Normal Operation
3.5
mA max
Power-Down
?A max
Full Power-Down
1
?A max
Partial Power-Down (Internal Ref)
350
See Power-Up Times Section
VDD = 3 V
Power Dissipation
Normal Operation
10.5
mW max
Auto Full Power-Down
See Power vs. Throughput Section
?W max
Throughput 1 kSPS
31.5
?W max
Throughput 10 kSPS
315
Throughput 100 kSPS
3.15
mW max
Partial Power-Down (Internal Ref)
1.05
mW max
?W max
Full Power-Down
3
NOTES
1
See Terminology.
2
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2 (V
= 2.7 V to 5.5 V, VREF = VDD [EXT] unless otherwise noted)
DD
Parameter
Y Version
Unit
Conditions/Comments
?s (max)
Power-Up Time of AD7811/AD7812 after Rising Edge of CONVST
tPOWER-UP
1.5
?s (max)
t1
2.3
Conversion Time
CONVST Pulsewidth
t2
20
ns (min)
t3
25
ns (min)
SCLK High Pulsewidth
t4
25
ns (min)
SCLK Low Pulsewidth
t53
5
ns (min)
RFS Rising Edge to SCLK Rising Edge Setup Time
t63
5
ns (min)
TFS Falling Edge to SCLK Falling Edge Setup Time
t73
10
ns (max)
SCLK Rising Edge to Data Out Valid
t8
10
ns (min)
DIN Data Valid to SCLK Falling Edge Setup Time
t9
5
ns (min)
DIN Data Valid after SCLK Falling Edge Hold Time
t103, 4
20
ns (max)
SCLK Rising Edge to DOUT High Impedance
DOUT High Impedance to CONVST Falling Edge
t11
100
ns (min)
NOTES
1
Sample tested to ensure compliance.
2
See Figures 16, 17 and 18.
These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V DD = 5 V ? 10% and
3
0.4 V or 2 V for VDD = 3 V ? 10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t  11, quoted in the Timing Characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
200 A
IOL
TO
OUTPUT
2.1V
PIN
CL
50pF
IOH
200 A
Figure 1. Load Circuit for Digital Output Timing Specifications
REV. B
?3?
AD7811/AD7812
ABSOLUTE MAXIMUM RATINGS*
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75?C/W
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . ?0.3 V to +7 V
Digital Input Voltage to DGND (CONVST, SCLK, RFS, TFS,
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215?C
DIN, A0) . . . . . . . . . . . . . . . . . . . . . . . ?0.3 V, VDD + 0.3 V
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220?C
Digital Output Voltage to DGND (DOUT)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.3 V, VDD + 0.3 V
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115?C/W
REFIN to AGND . . . . . . . . . . . . . . . . . . . ?0.3 V, VDD + 0.3 V
Analog Inputs
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215?C
VIN1?VIN4 (AD7811) . . . . . . . . . . . . . . ?0.3 V, VDD + 0.3 V
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220?C
VIN1?VIN8 (AD7812) . . . . . . . . . . . . . . ?0.3 V, VDD + 0.3 V
Storage Temperature Range . . . . . . . . . . . . ?65?C to +150?C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150?C
nent damage to the device. This is a stress rating only; functional operation of the
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
device at these or any other conditions above those listed in the operational
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105?C/W
sections of this specification is not implied. Exposure to absolute maximum rating
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . . 260?C
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Linearity
Package
Package
Model
Error
Descriptions
Options
? 1 LSB
AD7811YN
16-Lead Plastic DIP
N-16
? 1 LSB
AD7811YR
16-Lead Small Outline IC (SOIC)
R-16A
? 1 LSB
AD7811YRU
16-Lead Thin Shrink Small Outline Package (TSSOP)
RU-16
? 1 LSB
AD7812YN
20-Lead Plastic DIP
N-20
? 1 LSB
AD7812YR
20-Lead Small Outline IC (SOIC)
R-20A
? 1 LSB
AD7812YRU
20-Lead Thin Shrink Small Outline Package (TSSOP)
RU-20
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
WARNING!
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7811/AD7812 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
ESD SENSITIVE DEVICE
are recommended to avoid performance degradation or loss of functionality.
REV. B
?4?
AD7811/AD7812
PIN CONFIGURATIONS
DIP/SOIC/TSSOP
VREF
16 VDD
VREF  1
20 VDD
1
CREF
2
19 CONVST
CREF
15 CONVST
2
VIN1
14 SCLK
3
18 SCLK
VIN1
3
AD7811
AGND 4
13 DIN
17 DIN
AGND
4
TOP VIEW
AD7812
VIN2
VIN2
5 (Not to Scale) 12 DOUT
16 DOUT
5
TOP VIEW
VIN3
11 RFS
6
VIN3
15 RFS
6
(Not to Scale)
VIN4
10 TFS
VIN4
14 TFS
7
7
9 DGND
8
A0
VIN5
13 DGND
8
VIN6
9
12 A0
VIN7 10
11 VIN8
PIN FUNCTION DESCRIPTIONS
Pin(s)
Pin(s)
AD7811
AD7812
Mnemonic
Description
An external reference input can be applied here. When using an external precision
1
1
VREF
reference or VDD the EXTREF bit in the control register must be set to logic one. The
external reference input range is 1.2 V to VDD.
2
2
CREF
Reference Capacitor. A capacitor (10 nF) is connected here to improve the noise
performance of the on-chip reference.
3, 5?7
3, 5?11
VIN1?VIN4(8)
Analog Inputs. The analog input range is 0 V to VREF.
4
4
AGND
Analog Ground. Ground reference for track/hold, comparator, on-chip reference and
DAC.
8
12
A0
Package Address Pin. This Logic Input can be hardwired high or low. When used in
conjunction with the package address bit in the control register this input allows two
devices to share the same serial bus. For example a twelve channel solution can be
achieved by using the AD7811 and the AD7812 on the same serial bus.
9
13
DGND
Digital Ground. Ground reference for digital circuitry.
10
14
TFS
Transmit Frame Sync. The falling edge of this Logic Input tells the part that a new
control byte should be shifted in on the next 10 falling edges of SCLK.
11
15
RFS
Receive Frame Sync. The rising edge of this Logic Input is used to enable a counter in
the serial interface. It is used to provide compatibility with DSPs which use a continuous
serial clock and framing signal. In multipackage applications the RFS Pin can also be
used as a serial bus select pin. The serial interface will ignore the SCLK until it receives a
rising edge on this input. The counter is reset at the end of a serial read operation.
12
16
DOUT
Serial Data Output. Serial data is shifted out on this pin on the rising edge of the serial
clock. The output enters a High impedance condition on the rising edge of the 11th
SCLK pulse.
13
17
DIN
Serial Data Input. The control byte is read in at this input. In order to complete a
serial write operation 13 SCLK pulses need to be provided. Only the first 10 bits are
shifted in--see Serial Interface section.
14
18
SCLK
Serial Clock Input. An external serial clock is applied to this input to obtain serial data
from the AD7811/AD7812 and also to latch data into the AD7811/AD7812. Data is
clocked out on the rising edge of SCLK and latched in on the falling edge of SCLK.
CONVST
15
19
Convert Start. This is an edge triggered logic input. The Track/Hold goes into its Hold
Mode on the falling edge of this signal and a conversion is initiated. The state of this
pin at the end of conversion also determines whether the part is powered down or not.
See operating modes section of this data sheet.
16
20
VDD
Positive Supply Voltage 2.7 V to 5.5 V.
REV. B
?5?
AD7811/AD7812
TERMINOLOGY
usually distanced in frequency from the original sine waves
Signal to (Noise + Distortion) Ratio
while the third order terms are usually at a frequency close to
This is the measured ratio of signal to (noise + distortion) at the
the input frequencies. As a result, the second and third order
output of the A/D converter. The signal is the rms amplitude of
terms are specified separately. The calculation of the inter-
the fundamental. Noise is the rms sum of all nonfundamental
modulation distortion is as per the THD specification where it is
signals up to half the sampling frequency (fS/2), excluding dc.
the ratio of the rms sum of the individual distortion products to
The ratio is dependent upon the number of quantization levels
the rms amplitude of the fundamental expressed in dBs.
in the digitization process; the more levels, the smaller the
Channel-to-Channel Isolation
quantization noise. The theoretical signal to (noise + distor-
Channel-to-channel isolation is a measure of the level of
tion) ratio for an ideal N-bit converter with a sine wave input
crosstalk between channels. It is measured by applying a full-
is given by:
scale 20 kHz sine wave signal to all nonselected input channels
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
and determining how much that signal is attenuated in the selected
channel. The figure given is the worst case across all four or
Thus for a 10-bit converter, this is 62 dB.
eight channels for the AD7811 and AD7812 respectively.
Total Harmonic Distortion
Relative Accuracy
Total harmonic distortion (THD) is the ratio of the rms sum of
Relative accuracy, or endpoint nonlinearity, is the maximum
harmonics to the fundamental. For the AD7811 and AD7812
deviation from a straight line passing through the endpoints of
it is defined as:
the ADC transfer function.
V22 +V  3 +V  4 +V  52 +V  62
2
2
Differential Nonlinearity
THD (dB) = 20 log
This is the difference between the measured and the ideal
V1
1 LSB change between any two adjacent codes in the ADC.
where V1 is the rms amplitude of the fundamental and V2, V3,
Offset Error
V4, V5 and V6 are the rms amplitudes of the second through the
This is the deviation of the first code transition (0000 . . . 000)
sixth harmonics.
to (0000 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Peak Harmonic or Spurious Noise
Offset Error Match
Peak harmonic or spurious noise is defined as the ratio of the
This is the difference in Offset Error between any two channels.
rms value of the next largest component in the ADC output
Gain Error
spectrum (up to fS/2 and excluding dc) to the rms value of the
This is the deviation of the last code transition (1111 . . . 110)
fundamental. Normally, the value of this specification is
to (1111 . . . 111) from the ideal, i.e., VREF ? 1 LSB, after the
determined by the largest harmonic in the spectrum, but for
offset error has been adjusted out.
parts where the harmonics are buried in the noise floor, it will
be a noise peak.
Gain Error Match
This is the difference in Gain Error between any two channels.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
Track/Hold Acquisition Time
fb, any active device with nonlinearities will create distortion
Track/hold acquisition time is the time required for the output
products at sum and difference frequencies of mfa ? nfb where
of the track/hold amplifier to reach its final value, within
? 1/2 LSB, after the end of conversion (the point at which the
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the
track/hold returns to track mode). It also applies to situations
second order terms include (fa + fb) and (fa ? fb), while the
where a change in the selected input channel takes place or
third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb) and
where there is a step input change on the input voltage applied
(fa ? 2fb).
to the selected VIN input of the AD7811 or AD7812. It means
that the user must wait for the duration of the track/hold acquisi-
The AD7811 and AD7812 are tested using the CCIF standard
tion time after the end of conversion or after a channel change/
where two input frequencies near the top end of the input
step input change to VIN before starting another conversion, to
bandwidth are used. In this case, the second and third order
ensure that the part operates to specification.
terms are of different significance. The second order terms are
REV. B
?6?
AD7811/AD7812
Control Register (AD7811)
The Control Register is a 10-bit-wide, write only register. The Control Register is written to when the AD7811 receives a falling
edge on its TFS pin. The AD7811 will maintain the same configuration until a new control byte is written to the part. The control
register can be written to at the same time data is being read. This latter feature enhances throughput rates when software control is
being used or when the analog input channels are being changed frequently. The power-up default register contents are all zeros;
therefore, when the supplies are connected, the AD7811 is powered down by default.
Control Register AD7811
9
0
VIN4/AGND
DIFF/SGL
CONVST EXTREF
X*
CH1
CH0
A0
PD1
PD0
*This is a don't care bit.
A0
This is the package address bit. It is used in conjunction with the package address pin to allow two AD7811s to
share the same serial bus. The AD7811 can also share the same serial bus with the AD7812. When a control word
is written to the control register of the AD7811 the control word is ignored if the package address bit in the con-
trol byte does not match how the package address pin is hardwired. Only the serial port of the device that received
the last valid control byte, i.e., the address bit matched the address pin, will attempt to drive the serial bus on the
next serial read. When the part powers up this bit is set to 0.
PD1, PD0
These bits allow the AD7811 to be fully powered down and powered up. Bit combinations PD1 = PD0 = 0 and
PD1 = PD0 = 1 override the automatic power-down decision at the end of conversion. These bits also decide the
power-down mode when the AD7811 enters a power-down at the end of a conversion. There are two power-down
modes--Full Power-Down and Partial Power-Down. See Power-Down Options section of this data sheet.
PD1
PD0
Description
0
0
Full Power-Down of the AD7811
0
1
Partial Power-Down at the End of Conversion
1
0
Full Power-Down at the End of Conversion
1
1
Power-Up the AD7811
VIN4/AGND
The DIF/SGL bit in the control register must be set to 0 to use this option otherwise this bit is ignored. Setting
VIN4/AGND to 0 configures the analog inputs of the AD7811 as four single-ended analog inputs referenced to
analog ground (AGND). By setting this bit to 1 the input channels VIN1 to VIN3 are configured as three pseudo-
differential channels with respect to VIN4--see Table I.
DIF/SGL
This bit is used to configure the analog inputs as single ended or pseudo differential pairs. By setting this bit to 0
the analog inputs can be configured as single ended with respect to AGND, or pseudo differential with respect to
VIN4 as explained above. Setting this bit to 1 configures the analog input channels as two pseudo differential pairs
VIN1/VIN2 and VIN3/VIN4--see Table I.
These bits are used in conjunction with VIN4/AGND and DIF/SGL to select an analog input channel. The table
CH1, CH0
shows how the various channel selections are made--see Table I.
CONVST
Setting this bit to a logic one initiates a conversion. A conversion is initiated 400 ns after a write to the control
register has taken place. This allows a signal to be acquired even if the channel is changed and a conversion
initiated in the same serial write. The bit is reset after the end of a conversion.
EXTREF
This bit must be set to a logic one if the user wishes to use an external reference or use VDD as the reference.
When the external reference is selected the on chip reference circuitry powers down.
REV. B
?7?
AD7811/AD7812
Control Register (AD7812)
The Control Register is a 10-bit-wide, write only register. The Control Register is written to when the AD7812 receives a falling
edge on its TFS pin. The AD7812 will maintain the same configuration until a new control byte is written to the part. The control
register can be written to at the same time data is being read. This latter feature enhances throughput rates when software control is
being used or when the analog input channels are being changed frequently. The power-up default register contents are all zeros;
therefore, when the supplies are connected, the AD7812 is powered down by default.
Control Register AD7812
9
0
VIN8/AGND
DIFF/SGL
CONVST EXTREF
A0
PD1
PD0
CH2
CH1
CH0
A0
This is the package address bit. It is used in conjunction with the package address pin to allow two AD7812s to
share the same serial bus. The AD7812 can also share the same serial bus with the AD7811. When a control word
is written to the control register of the AD7812 the control word is ignored if the package address bit in the con-
trol byte does not match how the package address pin is hardwired. Only the serial port of the device which
received the last valid control byte, i.e., the address bit matched the address pin, will attempt to drive the serial bus
on the next serial read. When the part powers up this bit is set to 0.
PD1, PD0
These bits allow the AD7812 to be fully powered down and powered up. Bit combinations PD1 = PD0 = 0 and
PD1 = PD0 = 1 override the automatic power-down decision at the end of conversion. These bits also decide the
power-down mode when the AD7812 enters a power-down at the end of a conversion. There are two power-down
modes--Full Power-Down and Partial Power-Down. See Power-Down section of this data sheet.
PD1
PD0
Description
0
0
Full Power-Down of the AD7812
0
1
Partial Power-Down at the End of Conversion
1
0
Full Power-Down at the End of Conversion
1
1
Power-Up the AD7812
VIN8/AGND
The DIF/SGL bit in the control register must be set to 0 in order to use this option otherwise this bit is ignored.
Setting VIN8/AGND to 0 configures the analog inputs of the AD7812 as eight single-ended analog inputs
referenced to analog ground (AGND). By setting this bit to 1 the input channels VIN1 to VIN7 are configured
as seven pseudo differential channels with respect to VIN8--see Table II.
DIF/SGL
This bit is used to configure the analog inputs as single ended or pseudo differential pairs. By setting this bit to 0
the analog inputs can be configured as single ended with respect to AGND, or pseudo differential with respect to
VIN8 as explained above. Setting this bit to 1 configures the analog input channels as four pseudo differential pairs
VIN1/VIN2, VIN3/VIN4, VIN5/VIN6 and VIN7/VIN8--see Table II.
CH2, CH1, CH0 These bits are used in conjunction with VIN8/AGND and DIF/SGL to select an analog input channel. Table II
shows how the various channel selections are made.
CONVST
Setting this bit to a logic one initiates a conversion. A conversion is initiated 400 ns after a write to the control
register has taken place. This allows a signal to be acquired even if the channel is changed and a conversion initi-
ated in the same write operation. The bit is reset after the end of a conversion.
EXTREF
This bit must be set to a logic one if the user wishes to use an external reference or use VDD as the reference.
When the external reference is selected the on-chip reference circuitry powers down and the current consumption
is reduced by about 1 mA.
REV. B
?8?
AD7811/AD7812
Table I. AD7811 Channel Configurations
VIN4/AGND
DIF/SGL
CH1
CH0
Description
VIN1 Single-Ended with Respect to AGND
0
0
0
0
0
0
0
1
VIN2 Single-Ended with Respect to AGND
VIN3 Single-Ended with Respect to AGND
0
0
1
0
0
0
1
1
VIN4 Single-Ended with Respect to AGND
1
0
0
0
VIN1 Pseudo Differential with Respect to VIN4
1
0
0
1
VIN2 Pseudo Differential with Respect to VIN4
1
0
1
0
VIN3 Pseudo Differential with Respect to VIN4
X
1
0
0
VIN1(+) Pseudo Differential with Respect to VIN2(?)
VIN3(+) Pseudo Differential with Respect to VIN4(?)
X
1
0
1
X
1
1
0
Internal Test. SAR Input Equal to VREF/2
X
1
1
1
Internal Test. SAR Input Equal to VREF
Table II. AD7812 Channel Configurations
VIN8/AGND
DIF/SGL
CH2
CH1
CH0
Description
VIN1 Single-Ended with Respect to AGND
0
0
0
0
0
0
0
0
0
1
VIN2 Single-Ended with Respect to AGND
VIN3 Single-Ended with Respect to AGND
0
0
0
1
0
0
0
0
1
1
VIN4 Single-Ended with Respect to AGND
0
0
1
0
0
VIN5 Single-Ended with Respect to AGND
VIN6 Single-Ended with Respect to AGND
0
0
1
0
1
0
0
1
1
0
VIN7 Single-Ended with Respect to AGND
0
0
1
1
1
VIN8 Single-Ended with Respect to AGND
VIN1 Pseudo Differential with Respect to VIN8
1
0
0
0
0
1
0
0
0
1
VIN2 Pseudo Differential with Respect to VIN8
1
0
0
1
0
VIN3 Pseudo Differential with Respect to VIN8
1
0
0
1
1
VIN4 Pseudo Differential with Respect to VIN8
1
0
1
0
0
VIN5 Pseudo Differential with Respect to VIN8
1
0
1
0
1
VIN6 Pseudo Differential with Respect to VIN8
1
0
1
1
0
VIN7 Pseudo Differential with Respect to VIN8
X
1
0
0
0
VIN1(+) Pseudo Differential with Respect to VIN2(?)
VIN3(+) Pseudo Differential with Respect to VIN4(?)
X
1
0
0
1
X
1
0
1
0
VIN5(+) Pseudo Differential with Respect to VIN6(?)
X
1
0
1
1
VIN7(+) Pseudo Differential with Respect to VIN8(?)
Internal Test. SAR Input Equal to VREF/2
X
1
1
0
0
X
1
1
0
1
Internal Test. SAR Input Equal to VREF
REV. B
?9?
AD7811/AD7812
CIRCUIT DESCRIPTION
SUPPLY
2.7V TO 5.5V
Converter Operation
THREE-WIRE
The AD7811 and AD7812 are successive approximation analog-
SERIAL
10 F
0.1 F
10nF
INTERFACE
to-digital converters based around a charge redistribution DAC.
The ADCs can convert analog input signals in the range 0 V to
VDD  VREF CREF
VDD. Figures 2 and 3 show simplified schematics of the ADC.
SCLK
Figure 2 shows the ADC during its acquisition phase. SW2 is
VIN1
closed and SW1 is in position A, the comparator is held in a
DOUT
VIN2
balanced condition and the sampling capacitor acquires the
AD7811/
0V TO
DIN
?C/?P
signal on VIN.
AD7812
VREF
INPUT
VIN4(8)
CONVST
CHARGE
REDISTRIBUTION
RFS
DAC
SAMPLING
AGND
CAPACITOR
TFS
A
VIN
CONTROL
DGND
SW1
A0
LOGIC
ACQUISITION
B
PHASE
SW2
COMPARATOR
Figure 4. Typical Connection Diagram
AGND
CLOCK
OSC
VDD/3
Analog Input
Figure 5 shows an equivalent circuit of the analog input struc-
Figure 2. ADC Acquisition Phase
ture of the AD7811 and AD7812. The two diodes D1 and D2
When the ADC starts a conversion, see Figure 3, SW2 will
provide ESD protection for the analog inputs. Care must be
open and SW1 will move to position B causing the comparator
taken to ensure that the analog input signal never exceeds the
to become unbalanced. The Control Logic and the Charge
supply rails by more than 200 mV. This will cause these diodes
Redistribution DAC are used to add and subtract fixed amounts
to become forward biased and start conducting current into
of charge from the sampling capacitor to bring the comparator
the substrate. 20 mA is the maximum current these diodes can
back into a balanced condition. When the comparator is rebal-
conduct without causing irreversible damage to the part. How-
anced, the conversion is complete. The Control Logic generates
ever, it is worth noting that a small amount of current (1 mA)
the ADC output code. Figure 10 shows the ADC transfer
being conducted into the substrate due to an overvoltage on an
function.
unselected channel can cause inaccurate conversions on a
selected channel. The capacitor C2 in Figure 5 is typically about
4 pF and can primarily be attributed to pin capacitance. The
CHARGE
REDISTRIBUTION
resistor R1 is a lumped component made up of the on resistance
DAC
SAMPLING
of a multiplexer and a switch. This resistor is typically about
CAPACITOR
A
125 . The capacitor C1 is the ADC sampling capacitor and
VIN
CONTROL
has a capacitance of 3.5 pF.
SW1
LOGIC
B
CONVERSION
PHASE
COMPARATOR
VDD
SW2
AGND
CLOCK
OSC
VDD/3
D1
C1
R1
Figure 3. ADC Conversion Phase
3.5pF
C
125
VDD /3
VIN
TYPICAL CONNECTION DIAGRAM
2
D2
Figure 4 shows a typical connection diagram for the AD7811/
4pF
AD7812. The AGND and DGND are connected together at
CONVERSION PHASE ? SWITCH OPEN
TRACK PHASE ? SWITCH CLOSED
the device for good noise suppression. The serial interface is
implemented using three wires with RFS/TFS connected to
CONVST see Serial Interface section for more details. VREF is
Figure 5. Equivalent Analog Input Circuit
connected to a well decoupled VDD pin to provide an analog
The analog inputs on the AD7811 and AD7812 can be config-
input range of 0 V to VDD. If the AD7811 or AD7812 is not
ured as single ended with respect to analog ground (AGND),
sharing a serial bus with another AD7811 or AD7812 then A0
as pseudo differential with respect to a common, and also as
(package address pin) should be hardwired low. The default
pseudo differential pairs--see Control Register section.
power up value of the package address bit in the control register
is 0. For applications where power consumption is of concern,
the automatic power down at the end of a conversion should be
used to improve power performance. See Power-Down Options
section of the data sheet.
REV. B
?10?
AD7811/AD7812
An example of the pseudo differential scheme using the AD7811
Figure 8 shows the equivalent charging circuit for the sampling
is shown in Figure 6. The relevant bits in the AD7811 Control
capacitor when the ADC is in its acquisition phase. R2 repre-
Register are set as follows DIF/SGL = 1, CH1 = CH2 = 0, i.e.,
sents the source impedance of a buffer amplifier or resistive
VIN1 pseudo differential with respect to VIN2. The signal is
network; R1 is an internal multiplexer resistance, and C1 is the
applied to VIN1 but in the pseudo differential scheme the sam-
sampling capacitor. During the acquisition phase the sampling
pling capacitor is connected to VIN2 during conversion and not
capacitor must be charged to within a 1/2 LSB of its final value.
AGND as described in the Converter Operation section. This
The time it takes to charge the sampling capacitor (TCHARGE) is
input scheme can be used to remove offsets that exist in a sys-
given by the following formula:
tem. For example, if a system had an offset of 0.5 V the offset
TCHARGE = 7.6 ?(R2 + 125 ) ?3.5 pF
could be applied to VIN2 and the signal applied to VIN1. This has
the effect of offsetting the input span by 0.5 V. It is only pos-
R1
VIN+
R2
sible to offset the input span when the reference voltage is less
125
than VDD?OFFSET.
SAMPLING
C1
CAPACITOR
3.5pF
CHARGE
REDISTRIBUTION
Figure 8. Equivalent Sampling Circuit
DAC
SAMPLING
For small values of source impedance, the settling time associ-
VIN1
CAPACITOR
VIN+
ated with the sampling circuit (100 ns) is, in effect, the acquisi-
VIN1
CONTROL
tion time of the ADC. For example, with a source impedance
VOFFSET
LOGIC
(R2) of 10 the charge time for the sampling capacitor is
CONVERSION
VIN?
COMPARATOR
PHASE
approximately 4 ns. The charge time becomes significant for
CLOCK
VOFFSET
VIN2
source impedances of 2 kand greater.
OSC
VDD/3
AC Acquisition Time
In ac applications it is recommended to always buffer analog
Figure 6. Pseudo Differential Input Scheme
input signals. The source impedance of the drive circuitry must
When using the pseudo differential input scheme the signal on
be kept as low as possible to minimize the acquisition time of
VIN2 must not vary by more than a 1/2 LSB during the conver-
the ADC. Large values of source impedance will cause the THD
sion process. If the signal on VIN2 varies during conversion, the
to degrade at high throughput rates. In addition, better perfor-
conversion result will be incorrect. In single-ended mode the
mance can generally be achieved by using an External 1 nF
sampling capacitor is always connected to AGND during con-
capacitor on VIN.
version. Figure 7 shows the AD7811/AD7812 pseudo differen-
tial input being used to make a unipolar dc current measurement.
ON-CHIP REFERENCE
A sense resistor is used to convert the current to a voltage and
The AD7811 and AD7812 have an on-chip 2.5 V reference
the voltage is applied to the differential input as shown.
circuit. The schematic in Figure 9 shows how the reference
circuit is implemented. A 1.23 V bandgap reference is gained up
VDD
to provide a 2.5 V ? 2% reference voltage. The on-chip refer-
ence is not available externally (SW2 is open). An external refer-
VIN+
ence (1.2 V to VDD) can be applied at the VREF pin. However in
AD7811/
RSENSE
AD7812
order to use an external reference the EXTREF bit in the con-
VIN?
trol register (Bit 0) must first be set to a Logic 1. When EXTREF
RL
is set to a Logic 1 SW2 will close, SW3 will open and the ampli-
fier will power down. This will reduce the current consumption
of the part by about 1 mA. It is possible to use two different
reference voltages by selecting the on-chip reference or external
Figure 7. DC Current Measurement Scheme
reference.
DC Acquisition Time
CREF
The ADC starts a new acquisition phase at the end of a conver-
EXTERNAL
sion and ends on the falling edge of the CONVST signal. At the
CAPACITOR
VREF
end of a conversion a settling time is associated with the sam-
SW1
pling circuit. This settling time lasts approximately 100 ns. The
SW2
analog signal on VIN+ is also being acquired during this settling
1.23V
time. Therefore, the minimum acquisition time needed is