Ij

a
LC2MOS Complete 12-Bit
100 kHz Sampling ADC with DSP Interface
AD7878
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Complete ADC with DSP Interface, Comprising:
Track/Hold Amplifier with 2  s Acquisition Time
7  s A/D Converter
3 V Zener Reference
8-Word FIFO and Interface Logic
72 dB SNR at 10 kHz Input Frequency
Interfaces to High Speed DSP Processors, e.g.,
ADSP-2100, TMS32010, TMS32020
41 ns max Data Access Time
Low Power, 60 mW typ
APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
High Speed Modems
DSP Servo Control
GENERAL DESCRIPTION
The AD7878 is a fast, complete, 12-bit A/D converter with a
versatile DSP interface consisting of an 8-word, first-in, first-out
(FIFO) memory and associated control logic.
PRODUCT HIGHLIGHTS
The FIFO memory allows up to eight samples to be digitized
1. Complete A/D Function with DSP Interface
before the microprocessor is required to service the A/D con-
The AD7878 provides the complete function for digitizing
verter. The eight words can then be read out of the FIFO at
ac signals to 12-bit accuracy. The part features an on-chip
maximum microprocessor speed. A fast data access time of
track/hold, on-chip reference and 12-bit A/D converter. The
41 ns allows direct interfacing to DSP processors and high
additional feature of an 8-word FIFO reduces the high soft-
speed 16-bit microprocessors.
ware overheads associated with servicing interrupts in DSP
An on-chip status/control register allows the user to program the
processors.
effective length of the FIFO and contains the FIFO out of
2. Dynamic Specifications for DSP Users
range, FIFO empty and FIFO word count information.
The AD7878 is fully specified and tested for ac parameters,
The analog input of the AD7878 has a bipolar range of ? 3 V.
including signal-to-noise ratio, harmonic distortion and
The AD7878 can convert full power signals up to 50 kHz and is
intermodulation distortion. Key digital timing parameters
fully specified for dynamic parameters such as signal-to-noise
are also tested and specified over the full operating tempera-
ratio and harmonic distortion.
ture range.
The AD7878 is fabricated in Linear Compatible CMOS
3. Fast Microprocessor Interface
(LC2MOS), an advanced, mixed technology process that com-
Data access time of 41 ns is the fastest ever achieved in a
bines precision bipolar circuits with low power CMOS logic.
monolithic A/D converter, and makes the AD7878 compat-
The part is available in four package styles, 28-pin plastic and
ible with all modern 16-bit microprocessors and digital
hermetic dual-in-line package (DIP), leadless ceramic chip
signal processors.
carrier (LCCC) or plastic leaded chip carrier (PLCC).
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
use, nor for any infringements of patents or other rights of third parties
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Fax: 617/326-8703
? Analog Devices, Inc., 1997
(VDD = +5 V  5%, VCC = +5 V  5%, VSS = ?5 V  5%, AGND = DGND =
AD7878?SPECIFICATIONS
0 V, fCLK = 8 MHz. All Specifications TMIN to TMAX, unless otherwise noted.)
J, A
K, L, B  S
1
Parameter
Versions  Versions Version
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE2
Signal-to-Noise Ratio (SNR)3 @ 25?C
70
72
70
dB min
VIN = 10 kHz Sine Wave, fSAMPLE = 100 kHz
TMIN to TMAX
70
71
70
dB min
Typically 71.5 dB for 0 < VIN < 50 kHz
VIN = 10 kHz Sine Wave, fSAMPLE = 100 kHz
Total Harmonic Distortion (THD)
?80
?80
?78
dB max
Typically ?86 dB for 0 < VIN < 50 kHz
VIN = 10 kHz, fSAMPLE = 100 kHz
Peak Harmonic or Spurious Noise
?80
?80
?78
dB max
Typically ?86 dB for 0 < VIN < 50 kHz
Intermodulation Distortion (IMD)
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
Second Order Terms
?80
?80
?78
dB max
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
Third Order Terms
?80
?80
?78
dB max
?s max
Track/Hold Acquisition Time
2
2
2
See Throughput Rate Section
DC ACCURACY
Resolution
12
12
12
Bits
Minimum Resolution for Which
No Missing Codes are Guaranteed
12
12
12
Bits
? 1/2
? 1/4
? 1/2
Relative Accuracy
LSB typ
? 1/2
? 1/2
? 1/2
Differential Nonlinearity
LSB typ
?6
?6
?6
Bipolar Zero Error
LSB max
?6
?6
?6
Positive Full-Scale Error4
LSB max
?6
?6
?6
Negative Full-Scale Error4
LSB max
ANALOG INPUT
?3
?3
?3
Input Voltage Range
Volts
? 550
? 550
? 550
?A max
Input Current
REFERENCE OUTPUT5
REF OUT
3
3
3
V nom
REF OUT Error @ 25?C
? 10
? 10
? 10
mV max
? 15
? 15
? 15
TMIN to TMAX
mV max
Reference Load Sensitivity
(REF OUT/I)
?1
?1
?1
Reference Load Current Change (0 ?A?500 ?A).
mV max
Reference Load Should Not Be Changed
During Conversion
LOGIC INPUTS
VCC = +5 V ? 5%
+2.4
+2.4
+2.4
V min
Input High Voltage, VINH
VCC = +5 V ? 5%
+0.8
+0.8
+0.8
V max
Input Low Voltage, VINL
? 10
? 10
? 10
?A max
VIN = 0 to VCC
Input Current, IIN
Input Capacitance, CIN6
10
10
10
pF max
LOGIC OUTPUTS
ISOURCE 40 ?A
+2.7
+2.7
+2.7
V min
Output High Voltage, VOH
+0.4
+0.4
+0.4
V max
ISINK = 1.6 mA
Output Low Voltage, VOL
DB11?DB0
? 10
? 10
? 10
? 10
?A max
Floating State Leakage Current
Floating State Output Capacitance6
15
15
15
15
pF max
CONVERSION TIME
?s min/?s max
7/7.125
7/7.125
7/7.125
Assuming No External Read/Write Operations
?s min/?s max
7/9.250
7/9.250
7/9.250
Assuming 17 External Read/Write Operations
See Internal Comparator Timing Section
POWER REQUIREMENTS
? 5% for Specified Performance
+5
+5
+5
V nom
VDD
? 5% for Specified Performance
+5
+5
+5
V nom
VCC
? 5% for Specified Performance
?5
?5
?5
V nom
VSS
CS = DMWR = DMRD = 5 V
13
13
13
mA max
IDD
?A max
CS = DMWR = DMRD = 5 V
100
100
100
ICC
CS = DMWR = DMRD = 5 V
6
6
6
mA max
ISS
Power Dissipation
95.5
95.5
95.5
mW max
Typically 60 mW
NOTES
Temperature range as follows: J, K, L versions: 0?C to +70?C; A, B versions: ?25?C to +85?C; S version: ?55?C to +125?C.
1
VIN = ? 3 V. See Dynamic Specifications section.
2
3
SNR calculation includes distortion and noise components.
4
Measured with respect to the Internal Reference.
5
For capacitive loads greater than 50 pF a series resistor is required (see Internal Reference section).
Sample tested @ +25?C to ensure compliance.
6
Specifications subject to change without notice.
REV. A
?2?
AD7878
TIMING CHARACTERISTICS1 (V
=5V
5%, VCC = 5 V
5%, VSS = ?5 V
5%)
DD
Limit at TMIN, TMAX
Limit at TMIN, TMAX
Limit at TMIN, TMAX
Parameter (L Grade)
(J, K, A, B Grades)
(S Grade)
Units
Conditions/Comments
CLK IN to BUSY Low Propagation Delay
tl
65
65
75
ns max
CLK IN to BUSY High Propagation Delay
65
65
75
ns max
t2
CONVST Pulse Width
2 CLK IN Cycles
2 CLK IN Cycles
2 CLK IN Cycles
min
t3
CS to DMRD/REGISTER ENABLE Setup Time
0
0
0
ns min
t4
CS to DMRD/ REGISTER ENABLE Hold Time
0
0
0
ns min
t5
DMRD Pulse Width
45
60
60
ns min
t6
?s max
50
50
50
ADD0 to DMRD/REGISTER ENABLE Setup Time
16
16
16
ns min
t7
ADD0 to DMRD/REGISTER ENABLE Hold Time
0
0
0
ns min
t8
Data Access Time after DMRD
t92
41
57
57
ns min
t103
5
5
5
ns min
Bus Relinquish Time
45
45
45
ns max
42
42
55
ns min
REGISTER ENABLE Pulse Width
t11
?s max
50
50
50
20
20
30
ns min
Data Valid to REGISTER ENABLE Setup Time
t12
10
10
10
ns min
Data Hold Time after REGISTER ENABLE
t13
t142
41
57
57
ns min
Data Access Time after BUSY
tRESET
2 CLK IN Cycles
2 CLK IN Cycles
2 CLK IN Cycles
min
RESET Pulse Width
NOTES
Timing Specifications in bold print are 100% production tested. All other times are sample tested at +25 ?C to ensure compliance. All input signals are specified with
1
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t9 and t14 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t10 is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25?C unless otherwise stated)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . ?0.3 V to +7 V
VCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . ?0.3 V to +7 V
VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to ?7 V
VDD to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . ?0.3 V to VDD +0.3 V
VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . ?15 V to +15 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VDD
Digital Inputs to DGND
a. High-Z to VOH
b. High-Z to VOL
CLK IN, DMWR, DMRD, RESET,
Figure 1. Load Circuits for Access Time
CS, CONVST, ADD0 . . . . . . . . . . . . ?0.3 V to VDD +0.3 V
Digital Outputs to DGND
ALFL, BUSY . . . . . . . . . . . . . . . . . . ?0.3 V to VDD +0.3 V
Data Pins
DB11?DB0 . . . . . . . . . . . . . . . . . . . . ?0.3 V to VDD +0.3 V
Operating Temperature Range
J, K, L Versions . . . . . . . . . . . . . . . . . . . . . . . 0?C to +70?C
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . ?25?C to +85?C
S Version . . . . . . . . . . . . . . . . . . . . . . . . . ?55?C to +125?C
Storage Temperature Range . . . . . . . . . . . . ?65?C to +150?C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300?C
Power Dissipation (Any Package) to +75?C . . . . . . 1000 mW
Derates above +75?C by . . . . . . . . . . . . . . . . . . 10 mW/?C
a. VOH to High-Z
b. VOL to High-Z
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress rating only; functional operation of the
Figure 2. Load Circuits for Output Float Delay
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
WARNING!
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7878 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
?3?
AD7878
PIN FUNCTION DESCRIPTION
Pin
Pin
Number
Mnemonic
Function
11
ADD0
Address Input. This control input determines whether the word placed on the output data bus during a read operation is a data
word from the FIFO RAM or the contents of the status/control register. A logic low accesses the data word from Location 0 of
the FIFO while a logic high selects the contents of the register (see Status/Control Register section).
CS
12
Chip Select. Active low logic input. The device is selected when this input is active.
DMWR
Dam Memory Write. Active low logic input. DMWR is used in conjunction with CS low and ADD0 high to write data to the
13
status/control register. Corresponds to DMWR (ADSP-2100), R/W (MC68000, TMS32020), WE (TMS32010).
DMRD
Data Memory READ. Active low logic input. DMRD is used in conjunction with CS low to enable the three-state output buffers.
14
Corresponds directly to DMRD (ADSP-2100), DEN (TMS32010).
BUSY
Active Low Logic Output. This output goes low when the ADC receives a CONVST pulse and remains low until the track/hold
15
has gone into its hold mode. The three-state drivers of the AD7878 can be disabled while the BUSY signal is low (see Extended
READ/WRITE section). This is achieved by writing a logic 0 to DB5 (DISO) of the status/control register. Writing a logic 1 to
DB5 of the status/control register allows data to be accessed from the AD7878 while BUSY is low.
ALFL
16
FIFO Almost Full. A logic low indicates that the word count (i.e., number of conversion results) in the FIFO memory has
reached the programmed word count in the status/control register. ALFL is updated at the end of each conversion. The ALFL
output is reset to a logic high when a word is read from the FIFO memory and the word count is less than the preprogrammed
word count. It can also be set high by writing a logic 1 to DB7 (ENAF) of the status/control register.
17
DGND
Digital Ground. Ground reference for digital circuitry.
Digital supply voltage, +5 V ? 5%. Positive supply voltage for digital circuitry.
18
VCC
19
DB11
Data Bit 11 (MSB). Three-state TTL output. Coding for the data words in FIFO RAM is twos complement.
10?15
DB10?DB5
Data Bit 10 to Data Bit 5. Three-state TTL input/outputs.
16?19
DB4?DB1
Data Bit 4 to Data Bit 1. Three-state TTL outputs.
20
DB0
Data Bit 0 (LSB). Three-state TTL output.
Analog positive supply voltage, +5 V ? 5%.
21
VDD
22
AGND
Analog Ground. Ground reference for track/hold, reference and DAC.
23
REF OUT
Voltage Reference Output. The internal 3 V analog reference is provided at this pin. The external load capability of the reference
is 500 ?A.
Analog Input. Analog input range is ? 3 V.
24
VIN
Analog negative supply voltage, ?5 V ? 5%.
25
VSS
CONVST
26
Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and starts conversion.
The CONVST input is asynchronous to CLK IN and independent of CS, DMWR and DMRD.
RESET
Reset. Active low logic input. A logic low sets the words in FIFO memory to 1000 0000 0000 and resets the ALFL output and
27
status/control register.
28
CLK IN
Clock Input. TTL-compatible logic input. Used as the clock source for the A/D converter. The mark-space ratio of this clock can
vary from 35/65 to 65/35.
PIN CONFIGURATIONS
PLCC
DIP
LCCC
REV. A
?4?
AD7878
ORDERING GUIDE
DB10?DB8 (AFC2?AFC0)
Almost Full Word Count, Read/Write. The count value deter-
Signal-
Data
mines the number of words in the FIFO memory, which will
Temperature
to-Noise
Access
Package
cause ALFL to be set. When the FIFO word count equals the
1, 2
Options3
Model
Range
Ratio
Time
programmed count in these three bits, both the ALFL output
0?C to +70?C
and DB11 of the status register are set to a logic low. For ex-
AD7878JN
70 dB
57 ns
N-28
ample, when a code of 011 is written to these bits, ALFL is set
?25?C to +85?C
AD7878AQ
70 dB
57 ns
Q-28
?55?C to +125?C
when Location 0 through Location 3 of the FIFO memory
AD7878SQ
70 dB
57 ns
Q-28
0?C to +70?C
AD7878KN
72 dB
57 ns
N-28
contains valid data. AFC2 is the most significant bit of the word
?25?C to +85?C
AD7878BQ
72 dB
57 ns
Q-28
count. The count value can be read back if required.
0?C to +70?C
AD7878LN
72 dB
41 ns
N-28
?55?C to +125?C
AD7878SE4
70 dB
57 ns
E-28A
DB7 (ENAF)
0?C to +70?C
AD7878JP
70 dB
57 ns
P-28A
Enable Almost Full, Read/Write. Writing a 1 to this bit disables
0?C to +70?C
AD7878KP
72 dB
57 ns
P-28A
the ALFL output and status register bit DB11.
0?C to +70?C
AD7878LP
72 dB
41 ns
P-28A
DB6 (FOVR/RESET)
NOTES
FIFO Overrun/RESET, Read/Write. Reading a 1 from this bit
1
To order MIL-STD-883, Class B processed parts, add /883B to part number.
indicates that at least one sample has been discarded because
Contact our local sales office for military data sheet.
2
the FIFO memory is full. When the FIFO is full (i.e., contains
Analog Devices reserves the right to ship either ceramic (D-28) packages or
cerdip (Q-28) hermetic packages.
eight words) any further conversion results will be lost. Writing
3
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
a 1 to this bit causes a system RESET as per the RESET input
Carrier, Q = Cerdip.
(Pin 27).
4
Available to /883B processing only.
DB5 (FOOR/DISO)
STATUS/CONTROL REGISTER
FIFO Out of RANGE/Disable Outputs, Read/Write. Reading a
The status/control register serves the dual function of providing
1 from this bit indicates that at least one sample in the FIFO
control and monitoring the status of the FIFO memory. This
memory is out of range. Writing a 0 to this bit prevents the data
register is directly accessible through the data bus (DB11?DB0)
bus from becoming active while BUSY is low, regardless of the
with a read or write operation while ADD0 is high. A write
state of CS and DMRD.
operation to the status/control register provides control for the
ALFL output, bus interface and FIFO counter reset. This is
DB4 (FEMP)
normally done on power-up initialization. The FIFO memory
FIFO Empty, Read Only. Reading a 1 indicates there are no
address pointer is incremented after each conversion and com-
samples in the FIFO memory. When the FIFO is empty the
pared with a preprogrammed count in the status/control regis-
internal ripple-down effects of the FIFO are disabled and fur-
ter. When this preprogrammed count is reached, the ALFL
ther reads will continue to access the last valid data word in
output is asserted if the ENAF control bit is set to zero. This
Location 0.
ALFL can be used to interrupt the microprocessor after any
predetermined number of conversions (between 1 and 8). The
DB3 (SOOR)
status of the address pointer along with sample overrange and
Sample out of Range, Read Only. Reading a 1 indicates the next
ALFL status can be accessed at any time by reading the status/
sample to be read is out of range, i.e., the sample in Location 0
control register. Note: reading the status/control register does
of the FIFO.
not cause any internal data movement in the FIFO memory.
Status information for a particular word should be read from the
DB?DB0 (FCN2?FCN0)
status register before the data word is read from the FIFO
FIFO Word Count, Read Only. The value read from these bits
memory.
indicates the number of samples in the FIFO memory. For
example, reading 011 from these bits indicates that Location 0
STATUS/CONTROL REGISTER FUNCTION
through Location 3 contains valid data. Note: reading all 0s
DESCRIPTION
indicates there is either one word or no word in the FIFO
DB11 (ALFL)
memory; in this case the FIFO Empty determines if there is no
Almost Full Flag, Read only. This is the same as Pin 6 (ALFL
word in memory. FCN2 is the most significant bit.
output) status. A logic low indicates that the word count in
the FIFO memory has reached the preprogrammed count in bit
locations DB10?DB8. ALFL is updated at the end of conversion.
Table I. Status/Control Bit Function Description
BIT LOCATION
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ALFL
ENAF
STATUS INFORMATION (READ)
AFC2
AFC1
AFC0
FOVR  FOOR
FEMP
SOOR
FCN2
FCN1
FCN0
ENAF
RESET DISO
CONTROL FUNCTION (WRITE)
X
AFC2
AFC1
AFC0
X
X
X
X
X
RESET STATUS
1
0
0
0
0
0
0
1
0
0
0
0
X =DON'T CARE
REV. A
?5?
AD7878
INTERNAL FIFO MEMORY
INTERNAL COMPARATOR TIMING
The internal FIFO memory of the AD7878 consists of eight
The ADC clock, which is applied to CLK IN, controls the suc-
memory locations. Each word in memory contains 13 bits of
cessive approximation A/D conversion process. This clock is
information--12 bits of data from the conversion result and one
internally divided by four to yield a bit trial cycle time of 500 ns
additional bit which contains information as to whether the 12-
min (CLK IN = 8 MHz clock). Each bit decision occurs 25 ns
bit result is out of range or not. A block diagram of the AD7878
after the rising edge of this divided clock. The bit decision is
FIFO architecture is shown in Figure 3.
latched by the rising edge of an internal comparator strobe sig-
nal. There are 12-bit decisions, as in a normal successive ap-
proximation routine, and one extra decision that checks if the
input sample is out of range. In a normal successive approxima-
tion A/D converter, reading data from the device during conver-
sion can upset the conversion in progress. This is due to on-chip
transients, generated by charging or discharging the databus,
concurrent with a bit decision. The scheme outlined below and
shown in Figure 4 describes how the AD7878 overcomes this
problem.
The internal comparator strobe on the AD7878 is gated with
both DMRD and DMWR so that if a read or write operation
occurs when a bit decision is about to be made, the bit decision
point is deferred by one CLK IN cycle. In other words, if
DMRD or DMWR goes low (with CS low) at any time during
the CLK IN low time immediately prior to the comparator
Figure 3. Internal FIFO Architecture
strobing edge (tLOW of Figure 4), the bit trial is suspended for a
clock cycle. This makes sure that the bit decision is latched at a
The conversion result is gathered in the successive approxima-
time when the AD7878 is not attempting to charge or discharge
tion register (SAR) during conversion. At the end of conversion
the data bus, thereby ensuring that no spurious transients occur
this result is transferred to the FIFO memory. The FIFO ad-
internally near a bit decision point.
dress pointer always points to the top of memory, which is the
uppermost location containing valid data. The pointer is incre-
The decision point slippage mechanism is shown in Figure 4 for
mented after each conversion. A read operation from the FIFO
the MSB decision. Normally, the MSB decision occurs 25 ns
after the fourth rising CLK IN edge after CONVST goes high.
memory accesses data from the bottom of the FIFO, Location 0.
However, in the timing diagram of Figure 4, CS and DMRD or
On completion of the read operation, each data word moves
DMWR are low in the time period tLOW prior to the MSB deci-
down one location and the address pointer is decremented by
one. Therefore, each conversion result from the SAR enters at
sion point on the fourth rising edge. This causes the internal
the top of memory, propagates down with successive reads until
comparator strobe to be slipped to the fifth rising clock edge.
it reaches Location 0 from where it can be accessed by a micro-
The AD7878 will again check during a period tLOW prior to this
fifth rising clock edge; and if the CS and DMRD or DMWR are
processor read operation.
still low, the bit decision point will be slipped a further clock
The transfer of information from the SAR to the FIFO occurs in
cycle.
synchronization with the AD7878 input clock (CLK IN). The
propagation of data words down the FIFO is also synchronous
The conversion time for the ADC normally consists of the 13-
with this clock. As a result, a read operation to obtain data from
bit trials described above and one extra internal clock cycle during
the FIFO must also be synchronous with CLK IN to avoid
which data is written from the SAR to the FIFO. For an 8 MHz
input clock this results in a conversion time of 7 ?s. However,
Read/Write conflicts in the FIFO (i.e., reading from FIFO Loca-
tion 0 while it is being updated). This requires that the micro-
the software routine servicing the AD7878 has the potential to
processor clock and the AD7878 CLK IN are derived from the
read 16 times from the device during conversion--8 reads from
same source.
the FIFO and 8 reads from the status/control register. It also has
the potential to write once to the status/control register. If these
Figure 4. Operational Timing Diagram
REV. A
?6?
AD7878
operation with ADD0 low accesses data from the FIFO while a
17 (16 read plus 1 write) operations all occur during tLOW time
read with ADD0 high accesses data from the status/ control
periods, the conversion time will slip by 17 CLK IN cycles.
register.
Therefore, if read or write operations can occur during tLOW
periods, it means that the conversion time for the ADC can vary
from 7 ?s to 9.12 ?s (assuming 8 MHz CLK IN). This calcula-
tion assumes there is a slippage of one CLK IN cycle for each
read or write operation.
INITIATING A CONVERSION
Conversion is initiated on the AD7878 by asserting the CONVST
input. This CONVST input is an asynchronous input indepen-
dent of either the ADC or DSP clocks. This is essential for applica-
tions where precise sampling in time is important. In these applica-
tions the signal sampling must occur at exactly equal intervals to
minimize errors due to sampling uncertainty or jitter. In these cases
the CONVST input is driven from a tamer or some precise clock
source. On receipt of a CONVST pulse, the AD7878 acknowl-
edges by taking the BUSY output low. This BUSY output can be
used to ensure no bus activity while the track/hold goes from track
Figure 6. Basic Read Operation
to hold mode (see Extended Read/Write section). The CONVST
Basic Write Operation
input must stay low for at least two CLK IN periods. The track/
A basic write operation to the AD7878 status/control register
hold amplifier switches from the track to hold mode on the rising
consists of bringing CS and DMWR low with ADD0 high. In-
edge of CONVST and conversion is also initiated at this point.
ternally these signals are gated with CLK IN to provide an
The BUSY output returns high after the CONVST input goes high
internal REGISTER ENABLE signal (see Figure 7). The pulse
and the ADC begins its successive approximation routine. Once
width of this REGISTER ENABLE signal is effectively the
conversion has been initiated another conversion start should not
overlap between the CLK IN low time and the DMWR pulse.
be attempted until the full conversion cycle has been completed.
This may result in shorter write pulse widths, data setup times
Figure 5 shows the taming diagram for the conversion start.
and data hold times than those given by the microprocessor.
In applications where precise sampling is not critical, the
The timing on the AD7878 timing diagram of Figure 8 is there-
CONVST pulse can be generated from a microprocessor WR
fore given with respect to the internal REGISTER ENABLE
or RD line gated with a decoded address (different from the
signal rather than the DMWR signal.
AD7878 CS address). Note that the CONVST pulse width
must be a minimum of two AD7878 CLK IN cycles.
Figure 5. Conversion Start Timing Diagram
READ/WRITE OPERATIONS
Figure 7. DMWR Internal Logic
The AD7878 read/write operations consist of reading from the
FIFO memory and reading and writing from the status/control
register. These operations are controlled by the CS, DMRD,
DMWR and ADD0 logic inputs. A description of these operations
is given in the following sections. In addition to the basic read/write
operations there is an extended read/write operation. This can
occur if a read/write operation occurs during a CONVST pulse.
This extended read/write is intended for use with microproces-
sors that can be driven into a WAIT state, and the scheme is
recommended for applications where an external timer controls
the CONVST input asynchronously to the microprocessor read/
write operations.
Basic Read Operation
Figure 6 shows the timing diagram for a basic read operation on
Figure 8. Basic Write Operation
the AD7878. CS and DMRD going low accesses data from
either the status/control register or the FIFO memory. A read
REV. A
?7?
AD7878
Extended Read/Write Operation
AD7878 DYNAMIC SPECIFICATIONS
As described earlier, a read/write operation to the AD7878 can
The AD7878 is specified and 100% tested for dynamic perfor-
cause spurious on-chip transients. Should these transients occur
mance specifications rather than for traditional dc specifications
while the track/hold is going from track to hold mode, it may
such as Integral and Differential Nonlinearity. These ac specifi-
result in an incorrect value of VIN being held by the track/hold
cations provide information on the AD7878's effect on the spec-
amplifier. Because the CONVST input has asynchronous capa-
tral content of the input signal. Hence, the parameters for which
bility, a read/write operation could occur while CONVST is
the AD7878 is specified include SNR, Harmonic Distortion, inter-
modulation Distortion and Peak Harmonics. These terms are dis-
low. The AD7878 allows the read/write operation to occur but
cussed in more detail in the following sections.
has the facility to disable its three-state drivers so that there is
no data bus activity and, hence, no transients while the track/
Signal-to-Noise Ratio (SNR)
hold goes from track to hold.
SNR is the measured signal-to-noise ratio at the output of the
Writing a logic 0 to DB5 (DISO) of the status/control register
ADC. The signal is the rms magnitude of the fundamental.
prevents the output latches from being enabled while the
Noise is the rms sum of all the nonfundamental signals (excluding
AD7878 BUSY signal is low. If a microprocessor read/write
dc) up to half the sampling frequency (fS/2). SNR is dependent
operation can occur during the BUSY low time, the BUSY
upon the number of quantization levels used in the digitization
should be gated with CS of the AD7878 and this gated signal
process; the more levels, the smaller the quantization noise. The
used to stretch the instruction cycle using DMACK (ADSP-
theoretical signal-to-noise ratio for a sine wave input is given by
2100), READY (TMS32020) or DTACK (68000).
SNR = (6.02 N + 1.76) dB
(1)
When CONVST goes low, the AD7878 acknowledges it by
where N is the number of bits. Thus for an ideal 12-bit con-
bringing BUSY low on the next rising edge of CLK IN. With a
verter, SNR = 74 dB.
logic 0 in DB5, the AD7878 data bus cannot now be enabled. If
The output spectrum from the ADC is evaluated by applying a
a read/write operation now occurs, the BUSY and CS gated
sine-wave signal of very low distortion to the VIN input, which is
signal drives the microprocessor into a WAIT state, thereby
sampled at a 100 kHz sampling rate. A Fast Fourier Transform
extending the read/write operation. BUSY goes high on the
(FFT) plot is generated from which the SNR data can be ob-
second rising edge of CLK IN after CONVST goes high. The
tained. Figure 10 shows a typical 2048 point FFT plot of the
AD7878 data outputs are now enabled and the microprocessor
AD7878KN with an input signal of 25 kHz and a sampling
is released from its WAIT state, allowing it to complete its read/
frequency of 100 kHz. The SNR obtained from this graph is
write operation to the AD7878.
72.6 dB. It should be noted that the harmonics are included in
The microprocessor cycle time for the read/write operation is
the SNR calculation.
extended by the CONVST pulse width plus two CLK IN peri-
ods worst case. This is the maximum length of time for which
BUSY can be low. Assuming a CONVST pulse width of two
CLK IN periods and an 8 MHz CLK IN, the instruction cycle
is extended by 500 ns maximum. Figure 9 shows the timing
diagram for an extended read operation. In a similar manner, a
write operation will be extended if it occurs during a CONVST
pulse.
For processors that cannot be forced into a WAIT state, writing
a logic 1 into DB5 of the status/control register allows the out-
put latches to be enabled while BUSY is low. In this case BUSY
still goes low as before, but it would not be used to stretch the
read/write cycle and the instruction cycle continues as normal
(see Figures 6 and 8).
Figure 10. AD7878 FFT Plot
Effective Number of Bits
The formula given in (1) relates the SNR to the number of bits.
Rewriting the formula, as in (2), it is possible to get a measure of
performance expressed in effective number of bits (N). The
effective number of bits for a device can be calculated directly
from its measured SNR.
SNR ? 1.76
N=
(2)
6.02
Figure 9. Extended Read Operation
REV. A
?8?
AD7878
Figure 11 shows a typical plot of effective number of bits versus
frequency for an AD7878KN with a sampling frequency of
100 kHz. The effective number of bits typically falls between
11.7 and 11.85 corresponding to SNR figures of 72.2 and
73.1 dB.
Figure 11. Effective Number of Bits vs. Frequency
Figure 12. AD7878 IMD Plot
Harmonic Distortion
Histogram Plot
Harmonic Distortion is the ratio of the rms sum of harmonics to
When a sine wave of a specified frequency is applied to the VIN
the fundamental. For the AD7878, Total Harmonic Distortion
input of the AD7878 and several million samples are taken, it is
(THD) is defined as:
possible to plot a histogram showing the frequency of occur-
rence of each of the 4096 ADC codes. If a particular step is
(V  22 +V  32 +V  42 +V  52 +V  62 )
wider than the ideal 1 LSB width, then the code associated with
THD = 20 log
V1
that step will accumulate more counts than for the code for an
ideal step. Likewise, a step narrower than ideal will have fewer
where V1 is the rms amplitude of the fundamental and V2, V3,
counts. Missing codes are easily seen in the histogram plot because
V4, V5 and V6 are the rms amplitudes of the second to the sixth
a missing code means zero counts for a particular code. Large
harmonic. The THD is also derived from the FFT plot of the
spikes in the plot indicate large differential nonlinearity.
ADC output spectrum.
Figure 13 shows a histogram plot for the AD7878KN with a
Intermodulation Distortion
sampling frequency of 100 kHz and an input frequency of
With inputs consisting of sine waves at two frequencies, fa and
25 kHz. For a sine-wave input, a perfect ADC would produce a
fb, any active device with nonlinearities will create distortion
cusp probability density function described by the equation:
products at sum and difference frequencies of mfa + nfb where
m, n = 0, 1, 2, 3 . . . . , etc. Intermodulation terms are those for
1
p (V ) =
which neither m nor n is equal to zero. For example, the second
π ( A2 ?V 2 )
order terms include (fa + fb) and (fa ? fb) while the third order
terms include (2fa + fb), (2fa ? fb), (fa + 2fb) and (fa ? 2fb).
where A is the peak amplitude of the sine wave and p (V) is the
Using the CCIF standard, where two input frequencies near the
probability of occurrence at a voltage V. The histogram plot of
Figure 13 corresponds very well with this cusp shape. The ab-
top end of the input bandwidth are used, the second and third
sence of large spikes in this plot indicates small dynamic differ-
order terms are of different significance. The second order terms
are usually distanced in frequency from the original sine waves,
ential nonlinearity (the largest spike in the plot represents less
than 1/4 LSB of DNL error). The AD7878 has no missing
while the third order terms are usually at a frequency close to the
codes under these conditions since no code records zero counts.
input frequencies. As a result, the second and third order terms
are specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms am-
plitude of the fundamental expressed in dBs.
Intermodulation distortion is calculated using an FFT algorithm
but, in this case, the input consists of two equal amplitude, low
distortion sine waves. Figure 12 shows a typical IMD plot for
the AD7878.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to FS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification will be
determined by the largest harmonic in the spectrum, but for
Figure 13. AD7878 Histogram Plot
parts where the harmonics are buried in the noise floor the
largest peak will be a noise peak.
REV. A
?9?
AD7878
CONVERSION TIMING
ANALOG INPUT
The track-and-hold on the AD7878 goes from track-to-hold
Figure 15 shows the AD7878 analog input. The analog input
range is ? 3 V into an input resistance of typically 15 k. The
mode on the rising edge of CONVST, and the value of VIN at
this point is the value which will be converted. However, the
designed code transitions occur midway between successive
conversion actually sorts on the next rising edge of CLK IN
integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . .
after CONVST goes high. If CONVST goes high within ap-
FS?3/2 LSBs). The output code is 2s complement binary with
proximately 30 ns prior to a rising edge of CLK IN, that CLK
1 LSB = FS/4096 = 6 V/4096 = 1.46 mV. The ideal input/
IN edge will not be seen as the first CLK IN edge of the con-
output transfer function is shown in Figure 16.
version process, and conversion will not actually start until one
CLK IN cycle later. As a result, the conversion time (from
CONVST to FIFO update) will vary by one clock cycle de-
pending on the relationship between CONVST and CLK IN.
A conversion cycle normally consists of 56 CLK IN cycles
(assuming no read/write operations) which corresponds to a 7
As conversion time. If CONVST goes high within 30 ns prior
to a rising edge of CLK IN, the conversion time will consist of
57 CLK IN cycles, i.e., 7.125 ?s. This effect does not cause
track/hold jitter.
INTERNAL REFERENCE
Figure 15. AD7878 Analog Input
The AD7878 has an on-chip temperature compensated buried
Zener reference (see Figure 14) that is factory trimmed to 3 V
? 1%. Internally, it provides both the DAC reference and the
dc bias required for bipolar operation. The reference output is
available (REF OUT) and is capable of providing up to 500 ?A
to an external load.
Figure 16. Input/Output Transfer Function
Figure 14. AD7878 Reference Circuit
OFFSET AND FULL-SCALE ADJUSTMENT
The maximum recommended capacitance on REF OUT for
In most Digital Signal Processing (DSP) applications offset and
normal operation is 50 pF. If the reference is required for use
full-scale error have little or no effect on system performance.
external to the AD7878, it should be decoupled with a
Offset error can always be eliminated in the analog domain by
200 resistor in series with a parallel combination of a 10 ?F
ac coupling. Full-scale error effect is linear and does not cause
tantalum capacitor and a 0.1 ?F ceramic capacitor. These
problems as long as the input signal is within the full dynamic
decoupling components are required to remove voltage spikes
range of the ADC. Some applications may require that the input
caused by the internal operation of the AD7878.
signal span the full analog input dynamic range and, accord-
ingly, offset and full-scale error will have to be adjusted to zero.
TRACK-AND-HOLD AMPLIFIER
Where adjustment is required, offset must be adjusted before
The track-and-hold amplifier on the analog input of the
full-scale error. This is achieved by trimming the offset of the
AD7878 allows the ADC to accurately convert an input sine
op amp driving the analog input of the AD7878 while the input
wave of 6 V peak-peak amplitude to 12-bit accuracy. The input
voltage is 1/2 LSB below ground. The trim proc